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feat: Filter unsupported targets for the tests failing
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SergioGasquez committed Apr 29, 2024
1 parent f71398a commit 112d1d2
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Showing 3 changed files with 15 additions and 5 deletions.
2 changes: 2 additions & 0 deletions hil-test/tests/gpio.rs
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Expand Up @@ -4,6 +4,8 @@
//! GPIO2
//! GPIO4
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]

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2 changes: 2 additions & 0 deletions hil-test/tests/spi_full_duplex.rs
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Expand Up @@ -8,6 +8,8 @@
//!
//! Connect MISO (GPIO2) and MOSI (GPIO4) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]

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16 changes: 11 additions & 5 deletions hil-test/tests/uart.rs
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,8 @@
//!
//! Connect TX (GPIO2) and RX (GPIO4) pins.
//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3

#![no_std]
#![no_main]

Expand Down Expand Up @@ -108,11 +110,15 @@ mod tests {

#[cfg(not(feature = "esp32s2"))]
{
// 9600 baud, RC FAST clock source:
ctx.uart.change_baud(9600, ClockSource::RcFast, &ctx.clocks);
ctx.uart.write(7).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(7));
// TODO: Remove cfg once https://github.com/esp-rs/esp-hal/issues/1524 is solved
#[cfg(not(feature = "esp32c3"))]
{
// 9600 baud, RC FAST clock source:
ctx.uart.change_baud(9600, ClockSource::RcFast, &ctx.clocks);
ctx.uart.write(7).ok();
let read = block!(ctx.uart.read());
assert_eq!(read, Ok(7));
}

// 19,200 baud, XTAL clock source:
ctx.uart.change_baud(19_200, ClockSource::Xtal, &ctx.clocks);
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