NTHU-Logic Design Lab

• Lab1:Gate-Level Modeling
  • Basic
    • MUX
    • D-Latch
  • 4-bit 1-to-4 de-multiplexer
  • 4-bit simple crossbar switch with MUX/DMUX
  • 4-bit 4X4 crossbar
  • 1-bit toggle flip flop
• Lab2:Advanced Gate-Level Verilog
  • Basic
    • NAND gate only
    • 3-input majority gate
    • 1-bit full adder and half adder
  • 8-bit ripple carry adder (RCA)
  • Decode and execute
  • 8-bit carry-lookahead (CLA) Adder
  • 4-bit multiplier
  • An exhausted testbench design
  • Decode and execute (FPGA)
• Lab3:Sequential Circuits
  • Basic
    • Clock Divider
    • 128 x 8 Memory Array Memory
  • 4-bit Ping-Pong Counter
  • First-In First Out Circular Queue
  • Multi-Bank Memory
  • Round-Robin FIFO Arbiter
  • 4-bit Parameterized Ping-Pong Counter
  • 4-bit Paramterized Ping-Pong Counter（FPGA）
• Lab4:Finite State Machines
  • Basic
    • Moore Machine
    • Mealy Machine
    • Many-to-One Linear-Feedback Shift Register
    • One-to-Many Linear-Feedback Shift Register
  • Content-Addressable Memory Design
  • Scan Chain Design
  • Built-In Self Test
  • Mealy machine sequence detector
  • The 1A2B Game（FPGA）
• Lab5:Keyboard and Audio Modules
  • Basic
    • Keyboard sample code
    • Audio sample codes
  • Sliding Window Sequence Detector
  • Traffic Light Controller
  • Greatest Common Divisor
  • Booth Multiplier
  • Mixed Keyboard and Audio Modules Together（FPGA）
  • Vending Machine（FPGA）
• Lab6:Peripheral Components
  • Basic
    • VGA sample code
    • Mouse sample codes
  • Dual FPGA Communication（FPGA）
  • The Slot Machine（FPGA）
  • The Car（FPGA）