soc/intergration/soc/add_pcie: Add new status_width parameter.

enjoy-digital · Oct 2, 2024 · 5e89775 · 5e89775
1 parent 644ef7e
commit 5e89775
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -2395,7 +2395,7 @@ def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, addre
         with_dma_loopback     = True,
         with_dma_synchronizer = False,
         with_dma_monitor      = False,
-        with_dma_status       = False,
+        with_dma_status       = False, status_width=32,
         with_dma_table        = True,
         with_msi              = True, msi_type="msi", msi_width=32, msis={},
         with_ptm              = False,
@@ -2450,7 +2450,7 @@ def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, addre
                 with_loopback     = with_dma_loopback,
                 with_synchronizer = with_dma_synchronizer,
                 with_monitor      = with_dma_monitor,
-                with_status       = with_dma_status,
+                with_status       = with_dma_status, status_width=status_width,
                 with_table        = with_dma_table,
                 address_width     = address_width,
                 data_width        = data_width,