Cleanup Xilinx US/USP PHY integration. #123
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enjoy-digital
commented
Nov 7, 2023
enjoy-digital
commented
- Switch to .tcl for PHY generation (similar to 7-Series).
- Move AXI/TLP adaptation logic outside of pcie_support.v.
- Remove .xci files and duplicated code.
…similar to xilinx_us). Only for x4/x8 for now.
…and minor others cleanups.
…ernal signals to avoid hardcoded values.
…ip instead of pcie4_uscale_plus).
…ath to verilog_path in add_sources.
…rge enough for all cases.
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