Merge branch 'master' into xilinx_us_cleanup

.github/workflows/ci.yml

@@ -13,8 +13,18 @@ jobs:
       # Install Tools
       - name: Install Tools
         run: |
-          sudo apt-get install wget build-essential python3
-          pip3 install setuptools
+          sudo apt-get install wget build-essential
+
+      - name: Set up Python 3.9
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.9"
+          cache: "pip"
+          cache-dependency-path: "setup.py"
+
+      - name: Install Python dependencies
+        run: |
+          python3 -m pip install setuptools requests pexpect meson
 
       # Install (n)Migen / LiteX / Cores
       - name: Install LiteX

MANIFEST.in

@@ -1 +1,10 @@
-graft litepcie/software
+graft litepcie
+
+include CONTRIBUTORS
+include LICENSE
+
+graft doc
+
+prune bench
+prune examples
+prune test

README.md

@@ -46,6 +46,7 @@ Core:
 Frontend:
   - DMA (with Scatter-Gather).
   - MMAP (AXI/Wishbone Slave/Master).
+  - PTM (on Xilinx 7-Series/Gen2 X1 for now).
 
 Software:
   - Linux Driver (MMAP and DMA).

bench/acorn.py

@@ -12,6 +12,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex_boards.platforms import sqrl_acorn
 
 from litex.soc.cores.clock import S7PLL
@@ -21,18 +23,16 @@
 
 from litepcie.phy import s7pciephy
 
-class Open(Signal): pass
-
 # CRG ----------------------------------------------------------------------------------------------
 
-class _CRG(Module):
+class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.cd_sys = ClockDomain()
 
         # # #
 
         # PLL
-        self.submodules.pll = pll = S7PLL(speedgrade=-2)
+        self.pll = pll = S7PLL(speedgrade=-2)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
@@ -41,7 +41,7 @@ def __init__(self, platform, sys_clk_freq):
 class LitePCIeSoC(SoCMini):
     def __init__(self,  platform, sys_clk_freq=int(125e6)):
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq, ident="LitePCIe standalone example design on Acorn")

bench/fk33.py

@@ -11,6 +11,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex_boards.platforms import sqrl_fk33
 
 from litex.soc.cores.clock import USPPLL
@@ -26,14 +28,14 @@
 
 # CRG ----------------------------------------------------------------------------------------------
 
-class _CRG(Module):
+class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.cd_sys = ClockDomain()
 
         # # #
 
         # PLL
-        self.submodules.pll = pll = USPPLL(speedgrade=-2)
+        self.pll = pll = USPPLL(speedgrade=-2)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
@@ -53,45 +55,46 @@ def __init__(self, platform, speed="gen3", nlanes=4):
         SoCMini.__init__(self, platform, sys_clk_freq, ident=f"LitePCIe example design on FK33 ({speed}:x{nlanes})")
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # JTAGBone ---------------------------------------------------------------------------------
         self.add_jtagbone()
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = USPHBMPCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
+        self.pcie_phy = USPHBMPCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
             speed      = speed,
             data_width = data_width,
             bar0_size  = 0x20000,
         )
         self.pcie_phy.add_ltssm_tracer()
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
+        self.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
             endianness           = "little",
             max_pending_requests = 8
         )
 
         # Wishbone bridge
-        self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
+        self.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
             base_address = self.mem_map["csr"])
         self.bus.add_master(master=self.pcie_bridge.wishbone)
 
         # DMA0
-        self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         # DMA1
-        self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         self.add_constant("DMA_CHANNELS", 2)
+        self.add_constant("DMA_ADDR_WIDTH", 32)
 
         # MSI
-        self.submodules.pcie_msi = LitePCIeMSI()
+        self.pcie_msi = LitePCIeMSI()
         self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
         self.interrupts = {
             "PCIE_DMA0_WRITER":    self.pcie_dma0.writer.irq,

bench/kc705.py

@@ -11,6 +11,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex_boards.platforms import xilinx_kc705
 
 from litex.soc.cores.clock import S7MMCM
@@ -26,14 +28,14 @@
 
 # CRG ----------------------------------------------------------------------------------------------
 
-class _CRG(Module):
+class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys = ClockDomain()
+        self.cd_sys = ClockDomain()
 
         # # #
 
         # PLL
-        self.submodules.pll = pll = S7MMCM(speedgrade=-2)
+        self.pll = pll = S7MMCM(speedgrade=-2)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
@@ -53,44 +55,45 @@ def __init__(self, platform, speed="gen2", nlanes=4):
         SoCMini.__init__(self, platform, sys_clk_freq, ident=f"LitePCIe example design on KC705 ({speed}:x{nlanes})")
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # UARTBone ---------------------------------------------------------------------------------
         self.add_uartbone()
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
+        self.pcie_phy = S7PCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
             data_width = data_width,
             bar0_size  = 0x20000,
         )
         self.pcie_phy.add_ltssm_tracer()
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
+        self.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
             endianness           = "big",
             max_pending_requests = 8
         )
 
         # Wishbone bridge
-        self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
+        self.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
             base_address = self.mem_map["csr"])
         self.bus.add_master(master=self.pcie_bridge.wishbone)
 
         # DMA0
-        self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         # DMA1
-        self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         self.add_constant("DMA_CHANNELS", 2)
+        self.add_constant("DMA_ADDR_WIDTH", 32)
 
         # MSI
-        self.submodules.pcie_msi = LitePCIeMSI()
+        self.pcie_msi = LitePCIeMSI()
         self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
         self.interrupts = {
             "PCIE_DMA0_WRITER":    self.pcie_dma0.writer.irq,

bench/kcu105.py

@@ -11,6 +11,8 @@
 
 from migen import *
 
+from litex.gen import *
+
 from litex_boards.platforms import xilinx_kcu105
 
 from litex.soc.cores.clock import USPLL
@@ -26,14 +28,14 @@
 
 # CRG ----------------------------------------------------------------------------------------------
 
-class _CRG(Module):
+class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
 
         # # #
 
         # PLL
-        self.submodules.pll = pll = USPLL(speedgrade=-2)
+        self.pll = pll = USPLL(speedgrade=-2)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
 
@@ -52,45 +54,46 @@ def __init__(self, platform, speed="gen3", nlanes=4):
         SoCMini.__init__(self, platform, sys_clk_freq, ident=f"LitePCIe example design on KCU105 ({speed}:x{nlanes})")
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.crg = _CRG(platform, sys_clk_freq)
 
         # UARTBone ---------------------------------------------------------------------------------
         self.add_uartbone()
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = USPCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
+        self.pcie_phy = USPCIEPHY(platform, platform.request(f"pcie_x{nlanes}"),
             speed      = speed,
             data_width = data_width,
             bar0_size  = 0x20000,
         )
         self.pcie_phy.add_ltssm_tracer()
 
         # Endpoint
-        self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
+        self.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
             endianness           = "little",
             max_pending_requests = 8
         )
 
         # Wishbone bridge
-        self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
+        self.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,
             base_address = self.mem_map["csr"])
         self.bus.add_master(master=self.pcie_bridge.wishbone)
 
         # DMA0
-        self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         # DMA1
-        self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
+        self.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
             with_buffering = True, buffering_depth=1024,
             with_loopback  = True)
 
         self.add_constant("DMA_CHANNELS", 2)
+        self.add_constant("DMA_ADDR_WIDTH", 32)
 
         # MSI
-        self.submodules.pcie_msi = LitePCIeMSI()
+        self.pcie_msi = LitePCIeMSI()
         self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
         self.interrupts = {
             "PCIE_DMA0_WRITER":    self.pcie_dma0.writer.irq,