avsdpll_3v3 - OnChip PLL Clock Multiplier

Specifications

- ClockIn  5MHz  to 12.5MHz  at 1.8v
- ClockOut 40MHz to 100MHz   at 1.8v
- 8x multiplication

Parameter	Description	min	typ	max	Unit	Condition
VDD	Digital supply voltage		1.8		V	T=-40 to 150C
FCLKREF	Reference clock frequency	5	10	12.5	MHz
FCLKOUT	Output clock frequency	41.6	79.1	99.82	MHz	PLL mode, T=27C, VDD=1.8
DC	Duty Cycle	50.8	52.4	53.7	%	T=-40 to 150C
TSET	Settling time	3.8	8	8	us	start from EN_CP and report 2 values; one at FCLKOUT=40MHz and one at FCLKOUT=100MHz

This repository hosts relevant files on the IP.

1. Contents

0. Specifications - Specifications provided for the PLL.
1. Reports - Reports and presentations.
2. Schematic - Schematic of different blocks.
3. Layout - Layout of different blocks.
4. Misc - Images

2. Pre-layout Simulation of PLL

1. Input Frequency (F_in) = 5MHz

Locking in

8x clock

2. Input Frequency (F_in) = 10MHz

Locking in

8x clock

3. Layout

PFD

VCO

DIV2

DIV8

Due to the limitaions of OSU180 the chargepump layout was not made.

4. Post-layout Simulation of PLL

1. Input Frequency (F_in) = 5MHz

Locking in

8x clock

2. Input Frequency (F_in) = 10MHz

Locking in

8x clock

6. Tools Used

1. Ngspice
2. magic

7. Future work

1. Porting this IP to SKY130.
2. Improve area efficiency.
3. Add biasing current.
4. Improve jitter and lock in time.

8. Author

• Abel Joseph John, B.Tech in ECE, NSS College of Engineering, Palakkad

9. Acknowledgments & Thanks

• Kunal Promode Ghosh, for mentoring and guidance.
• Philipp Gühring, for helping out with tools.
• R. Timothy Edwards, for creating awesome OpenSource tools.
• Prof. R Jacob Baker, for his textbook on CMOS design.