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Atomic-free JNI work #2039

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Jun 1, 2018
Merged

Atomic-free JNI work #2039

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24 changes: 6 additions & 18 deletions runtime/compiler/p/codegen/PPCJNILinkage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -728,18 +728,11 @@ void TR::PPCJNILinkage::releaseVMAccessAtomicFree(TR::Node* callNode, TR::Regist
generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, callNode, tempReg1, 1);
generateMemSrc1Instruction(cg(), TR::InstOpCode::Op_st, callNode, new (trHeapMemory()) TR::MemoryReference(metaReg, (int32_t)offsetof(struct J9VMThread, inNative), TR::Compiler->om.sizeofReferenceAddress(), cg()), tempReg1);
#if !defined(J9VM_INTERP_ATOMIC_FREE_JNI_USES_FLUSH)
generateInstruction(cg(), TR::InstOpCode::sync, callNode); // Necessary?
generateInstruction(cg(), TR::InstOpCode::sync, callNode);
#endif /* !J9VM_INTERP_ATOMIC_FREE_JNI_USES_FLUSH */
generateTrg1MemInstruction(cg(), TR::InstOpCode::Op_load, callNode, tempReg1, new (trHeapMemory()) TR::MemoryReference(metaReg, fej9->thisThreadGetPublicFlagsOffset(), TR::Compiler->om.sizeofReferenceAddress(), cg()));
if (J9_PUBLIC_FLAGS_VM_ACCESS >= LOWER_IMMED && J9_PUBLIC_FLAGS_VM_ACCESS <= UPPER_IMMED)
generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::andi_r, callNode, tempReg2, tempReg1, cr0Reg, J9_PUBLIC_FLAGS_VM_ACCESS);
else
{
loadConstant(cg(), callNode, J9_PUBLIC_FLAGS_VM_ACCESS, tempReg2);
// FIXME: Apparently I'm the first one to ever use a Trg1Src2 record-form instruction...
// ctor for Trg1Src2 + condReg only has the preced form, if you don't pass a preceding instruction the following instruction will end up as the first instruction after the prologue
generateTrg1Src2Instruction(cg(), TR::InstOpCode::and_r, callNode, tempReg2, tempReg1, tempReg2, cr0Reg, /* FIXME */ cg()->getAppendInstruction());
}
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Although not applicable anymore, andis_r instruction can be used for the case where J9_PUBLIC_FLAGS_VM_ACCESS falls in the upper 16-bit.

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On the off chance we ever feel the need to change the bit value, we can re-assess. It didn't seem like a good idea to maintain a bunch of dead code in these functions. I think every platform will be able to represent 0x20 as an immediate today.

TR_ASSERT_FATAL(J9_PUBLIC_FLAGS_VM_ACCESS >= LOWER_IMMED && J9_PUBLIC_FLAGS_VM_ACCESS <= UPPER_IMMED, "VM access bit must be immediate");
generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::Op_cmpli, callNode, cr0Reg, tempReg1, J9_PUBLIC_FLAGS_VM_ACCESS);

TR::SymbolReference *jitReleaseVMAccessSymRef = comp()->getSymRefTab()->findOrCreateReleaseVMAccessSymbolRef(comp()->getJittedMethodSymbol());
TR::LabelSymbol *releaseVMAcessSnippetLabel = cg()->lookUpSnippet(TR::Snippet::IsHelperCall, jitReleaseVMAccessSymRef);
Expand All @@ -762,16 +755,11 @@ void TR::PPCJNILinkage::acquireVMAccessAtomicFree(TR::Node* callNode, TR::Regist
generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, callNode, tempReg1, 0);
generateMemSrc1Instruction(cg(), TR::InstOpCode::Op_st, callNode, new (trHeapMemory()) TR::MemoryReference(metaReg, (int32_t)offsetof(struct J9VMThread, inNative), TR::Compiler->om.sizeofReferenceAddress(), cg()), tempReg1);
#if !defined(J9VM_INTERP_ATOMIC_FREE_JNI_USES_FLUSH)
generateInstruction(cg(), TR::InstOpCode::sync, callNode); // Necessary?
generateInstruction(cg(), TR::InstOpCode::sync, callNode);
#endif /* !J9VM_INTERP_ATOMIC_FREE_JNI_USES_FLUSH */
generateTrg1MemInstruction(cg(), TR::InstOpCode::Op_load, callNode, tempReg1, new (trHeapMemory()) TR::MemoryReference(metaReg, fej9->thisThreadGetPublicFlagsOffset(), TR::Compiler->om.sizeofReferenceAddress(), cg()));
if (J9_PUBLIC_FLAGS_VM_ACCESS >= LOWER_IMMED && J9_PUBLIC_FLAGS_VM_ACCESS <= UPPER_IMMED)
generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::Op_cmpli, callNode, cr0Reg, tempReg1, J9_PUBLIC_FLAGS_VM_ACCESS);
else
{
loadConstant(cg(), callNode, J9_PUBLIC_FLAGS_VM_ACCESS, tempReg2);
generateTrg1Src2Instruction(cg(), TR::InstOpCode::Op_cmpli, callNode, cr0Reg, tempReg1, tempReg2);
}
TR_ASSERT_FATAL(J9_PUBLIC_FLAGS_VM_ACCESS >= LOWER_IMMED && J9_PUBLIC_FLAGS_VM_ACCESS <= UPPER_IMMED, "VM access bit must be immediate");
generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::Op_cmpli, callNode, cr0Reg, tempReg1, J9_PUBLIC_FLAGS_VM_ACCESS);

TR::SymbolReference *jitAcquireVMAccessSymRef = comp()->getSymRefTab()->findOrCreateAcquireVMAccessSymbolRef(comp()->getJittedMethodSymbol());
TR::LabelSymbol *acquireVMAcessSnippetLabel = cg()->lookUpSnippet(TR::Snippet::IsHelperCall, jitAcquireVMAccessSymRef);
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2 changes: 2 additions & 0 deletions runtime/compiler/x/amd64/codegen/AMD64JNILinkage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1130,6 +1130,7 @@ void TR::AMD64JNILinkage::releaseVMAccessAtomicFree(TR::Node *callNode)
TR::LabelSymbol *longReleaseSnippetLabel = generateLabelSymbol(cg());
TR::LabelSymbol *longReleaseRestartLabel = generateLabelSymbol(cg());

TR_ASSERT_FATAL(J9_PUBLIC_FLAGS_VM_ACCESS <= 0x7fffffff, "VM access bit must be immediate");
generateRegImmInstruction(CMP4RegImm4, callNode, scratchReg1, J9_PUBLIC_FLAGS_VM_ACCESS, cg());
generateLabelInstruction(JNE4, callNode, longReleaseSnippetLabel, cg());

Expand Down Expand Up @@ -1185,6 +1186,7 @@ void TR::AMD64JNILinkage::acquireVMAccessAtomicFree(TR::Node *callNode)
TR::LabelSymbol *longAcquireSnippetLabel = generateLabelSymbol(cg());
TR::LabelSymbol *longAcquireRestartLabel = generateLabelSymbol(cg());

TR_ASSERT_FATAL(J9_PUBLIC_FLAGS_VM_ACCESS <= 0x7fffffff, "VM access bit must be immediate");
generateRegImmInstruction(CMP4RegImm4, callNode, scratchReg1, J9_PUBLIC_FLAGS_VM_ACCESS, cg());
generateLabelInstruction(JNE4, callNode, longAcquireSnippetLabel, cg());

Expand Down