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Deprecate HPR support #3654

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Mar 19, 2019
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186 changes: 0 additions & 186 deletions compiler/codegen/CodeGenRA.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1260,8 +1260,6 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,
const bool canExitEarly = !rc->canBeReprioritized();
TR_BitVector alreadyAssignedOnEntry(self()->comp()->getSymRefCount(), self()->trMemory(), stackAlloc, growable);
TR_BitVector alreadyAssignedOnExit(self()->comp()->getSymRefCount(), self()->trMemory(), stackAlloc, growable);
bool hprSimulated = false;
bool hprColdBlockSkipped = false;

TR_BitVector blocksToVisit = rc->getBlocksLiveOnEntry();
blocksToVisit |= rc->getBlocksLiveOnExit();
Expand Down Expand Up @@ -1295,11 +1293,6 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,

TR::Block *block = allBlocks[blockIterator.getNextElement()];

// do not assign HPR to candidate if we skipped any block simulation for correctness
if (!block->isExtensionOfPreviousBlock() && blockIsIgnorablyCold(block, self()))
{
hprColdBlockSkipped = true;
}
if (!block->isExtensionOfPreviousBlock() && !blockIsIgnorablyCold(block, self()))
{
// This block starts an extended BB.
Expand Down Expand Up @@ -1381,24 +1374,7 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,
// Perform the simulation for current block and accumulate into highWaterMark
//
TR_RegisterPressureSummary summary(state._gprPressure, state._fprPressure, state._vrfPressure);
if (self()->supportsHighWordFacility())
{
TR::DataType dtype = rc->getSymbolReference()->getSymbol()->getDataType();
if (dtype == TR::Int8 ||
dtype == TR::Int16 ||
dtype == TR::Int32)
{
// unless proven, candidate is HPR eligible
state.setCandidateIsHPREligible(true);
}
else
{
state.setCandidateIsHPREligible(false);
summary.spill(TR_hprSpill, self());
}
}
self()->simulateBlockEvaluation(block, &state, &summary);
hprSimulated = true;
highWaterMark.accumulate(summary);

#if defined(CACHE_CANDIDATE_SPECIFIC_RESULTS)
Expand Down Expand Up @@ -1691,51 +1667,6 @@ OMR::CodeGenerator::pickRegister(TR_RegisterCandidate *rc,
}
}

if (self()->supportsHighWordFacility())
{
TR_BitVector HPRMasks = *self()->getGlobalRegisters(TR_hprSpill, self()->comp()->getMethodSymbol()->getLinkageConvention());
// We cannot assign an HPR if the corresponding GPR is alive.
// There is no safe way to anticipate whether instruction selection will clobber the High word
// e.g. generating 64-bit instructions for long arithmetics on 32-bit platform
// todo: maybe try checking candidate data type while assigning GPR? only clobber HPR candidate
// if the GPR candidate is long

if (remainingRegisters.intersects(HPRMasks))
{
for (int i = self()->getFirstGlobalGPR(); i < self()->getFirstGlobalHPR(); ++i)
{
if (!remainingRegisters.isSet(i))
{
TR_GlobalRegisterNumber highWordReg = self()->getGlobalHPRFromGPR(i);
if (self()->traceSimulateTreeEvaluation())
{
traceMsg(self()->comp(), " %s is not available, rejecting %s\n",
self()->getDebug()->getGlobalRegisterName(i), self()->getDebug()->getGlobalRegisterName(highWordReg));
}
remainingRegisters.reset(highWordReg);
}
}
}
// hack: always give priorities to HPR over GPR
// if any HPR candidate is present
if (remainingRegisters.intersects(HPRMasks))
{
TR::DataType dtype = rc->getSymbolReference()->getSymbol()->getDataType();
if (hprSimulated && !hprColdBlockSkipped)
{
if (self()->traceSimulateTreeEvaluation())
{
traceMsg(self()->comp(), " HPR candidates are available, rejecting all GPR\n");
remainingRegisters &= HPRMasks;
}
}
else
{
// if simulation did not happen, do not use hpr (cold blocks etc)
remainingRegisters -= HPRMasks;
}
}
}
if (self()->traceSimulateTreeEvaluation())
{
traceMsg(self()->comp(), " final registers: ");
Expand Down Expand Up @@ -2628,37 +2559,6 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
return;
}

if (self()->supportsHighWordFacility())
{
// 390 Highword, maybe move this below to else .hasRegister?
if (self()->isCandidateLoad(node, state))
{
if (node->getOpCodeValue() == TR::iload)
{
//potential HPR candidate
//state->setCandidateIsHPREligible(true);
node->setIsHPREligible();
}
else
{
// not HPR candidate
state->setCandidateIsHPREligible(false);
summary->spill(TR_hprSpill, self());
}
}
// if candidate is an object ref
if (state->_candidate && node->getOpCode().hasSymbolReference())
{
if (node->getOpCode().isRef() &&
node->getSymbolReference() == state->_candidate->getSymbolReference())
{
// not HPR candidate
state->setCandidateIsHPREligible(false);
summary->spill(TR_hprSpill, self());
}
}
}

TR_SimulatedNodeState &nodeState = self()->simulatedNodeState(node);
if (nodeState.hasRegister())
{
Expand Down Expand Up @@ -2753,63 +2653,12 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
traceMsg(self()->comp(), " ++%s", self()->getDebug()->getName(child));
}

if (self()->supportsHighWordFacility())
{
// first time visiting this node, clear the flag
if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
{
node->resetIsHPREligible();
}
}
self()->simulateNodeEvaluation(node, state, summary);

if (self()->supportsHighWordFacility())
{
bool needToCheckHPR = false;
for (uint16_t i = 0; i < node->getNumChildren(); i++)
{
TR::Node *child = node->getChild(i);
if (child->getIsHPREligible())
{
//traceMsg(comp(), " child %d has isHPREligible set", i);
needToCheckHPR = true;
}
}

// if enableHighwordRA 390
if (needToCheckHPR && state->getCandidateIsHPREligible())
{
if (node->isEligibleForHighWordOpcode())
{
//traceMsg(comp(), " hpr");
}
else
{
//traceMsg(comp(), " !hpr");
node->resetIsHPREligible();
state->setCandidateIsHPREligible(false);
summary->spill(TR_hprSpill, self());
}
}

if (node->getIsHPREligible())
{
//traceMsg(comp(), " assignedToHPR");
}
}
node->setFutureUseCount(originalRefcount); // Parent will decrement

}
else
{
if (self()->supportsHighWordFacility())
{
// first time visiting this node, clear the flag
if (node->getVisitCount() == state->_visitCountForInit && !self()->isCandidateLoad(node, state))
{
node->resetIsHPREligible();
}
}
// Some kinds of nodes very commonly use temporaries, and sometimes
// the number of temporaries depends on the registers used by
// children, so compute this while the children are still live.
Expand All @@ -2830,41 +2679,6 @@ OMR::CodeGenerator::simulateTreeEvaluation(TR::Node *node, TR_RegisterPressureSt
}

self()->simulateNodeEvaluation(node, state, summary);

if (self()->supportsHighWordFacility())
{
bool needToCheckHPR = false;
for (uint16_t i = 0; i < node->getNumChildren(); i++)
{
TR::Node *child = node->getChild(i);
if (child->getIsHPREligible())
{
//traceMsg(comp(), " child %d has isHPREligible set", i);
needToCheckHPR = true;
}
}

if (needToCheckHPR && state->getCandidateIsHPREligible())
{
// if enableHighwordRA 390
if (node->isEligibleForHighWordOpcode())
{
//traceMsg(comp(), " hpr");
}
else
{
node->resetIsHPREligible();
state->setCandidateIsHPREligible(false);
summary->spill(TR_hprSpill, self());
//traceMsg(comp(), " !hpr");
}
}

if (node->getIsHPREligible())
{
//traceMsg(comp(), " assignedToHPR");
}
}
}

// Accumulate the current state into the summary
Expand Down
6 changes: 0 additions & 6 deletions compiler/codegen/GCStackMap.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -224,11 +224,6 @@ class TR_GCStackMap
uint32_t info) {_registerMap.maskRegistersWithInfoBits(mask, info);}
void setInfoBits(uint32_t info) {_registerMap.setInfoBits(info);}

void setHighWordRegisterBits(uint32_t bits) {_registerMap.setHighWordRegisterBits(bits);}
void resetHighWordRegistersBits(uint32_t bits) {_registerMap.resetHighWordRegisterBits(bits);}
uint32_t getHighWordRegisterMap() {return _registerMap.getHPRMap();}
void clearHighWordRegisterMap() {_registerMap.emptyHPR();}

uint32_t getRegisterSaveDescription() {return _registerMap.getRegisterSaveDescription();}
void setRegisterSaveDescription(uint32_t bits) {_registerMap.setRegisterSaveDescription(bits);}

Expand Down Expand Up @@ -273,7 +268,6 @@ class TR_GCStackMap
memcpy(newMap->_liveMonitorBits, getLiveMonitorBits(), getMapSizeInBytes());
}
newMap->setRegisterBits(getRegisterMap());
newMap->setHighWordRegisterBits(getHighWordRegisterMap());
return newMap;
}

Expand Down
16 changes: 1 addition & 15 deletions compiler/codegen/OMRCodeGenerator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1098,7 +1098,7 @@ OMR::CodeGenerator::isGlobalVRF(TR_GlobalRegisterNumber n)
bool
OMR::CodeGenerator::isGlobalFPR(TR_GlobalRegisterNumber n)
{
return !self()->isGlobalGPR(n) && !self()->isGlobalHPR(n);
return !self()->isGlobalGPR(n);
}

TR_BitVector *
Expand All @@ -1123,7 +1123,6 @@ bool OMR::CodeGenerator::supportsInternalPointers()
return self()->internalPointerSupportImplemented();
}


uint16_t
OMR::CodeGenerator::getNumberOfGlobalRegisters()
{
Expand All @@ -1133,25 +1132,12 @@ OMR::CodeGenerator::getNumberOfGlobalRegisters()
return _lastGlobalFPR + 1;
}


#ifdef TR_HOST_S390
uint16_t OMR::CodeGenerator::getNumberOfGlobalGPRs()
{
if (self()->supportsHighWordFacility())
{
return _firstGlobalHPR;
}
return _lastGlobalGPR + 1;
}
#endif

int32_t OMR::CodeGenerator::getMaximumNumberOfGPRsAllowedAcrossEdge(TR::Block *block)
{
TR::Node *node = block->getLastRealTreeTop()->getNode();
return self()->getMaximumNumberOfGPRsAllowedAcrossEdge(node);
}


TR::Register *OMR::CodeGenerator::allocateCollectedReferenceRegister()
{
TR::Register * temp = self()->allocateRegister();
Expand Down
17 changes: 0 additions & 17 deletions compiler/codegen/OMRCodeGenerator.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,6 @@ enum TR_SpillKinds // For register pressure simulation
{
// Mandatory spill kinds are certain to cause a spill to memory
//
TR_hprSpill, // zGryphon 390 All integer highword regs
TR_gprSpill, // All integer regs
TR_fprSpill, // All floating-point regs
TR_vrfSpill, // All vector regs
Expand Down Expand Up @@ -918,14 +917,6 @@ class OMR_EXTENSIBLE CodeGenerator
TR_GlobalRegisterNumber getLastGlobalGPR() {return _lastGlobalGPR;}
TR_GlobalRegisterNumber setLastGlobalGPR(TR_GlobalRegisterNumber n) {return (_lastGlobalGPR = n);}

TR_GlobalRegisterNumber getFirstGlobalHPR() {return _firstGlobalHPR;}
TR_GlobalRegisterNumber setFirstGlobalHPR(TR_GlobalRegisterNumber n) {return (_firstGlobalHPR = n);}
TR_GlobalRegisterNumber getLastGlobalHPR() {return _lastGlobalHPR;}
TR_GlobalRegisterNumber setLastGlobalHPR(TR_GlobalRegisterNumber n) {return (_lastGlobalHPR = n);}

TR_GlobalRegisterNumber getGlobalHPRFromGPR (TR_GlobalRegisterNumber n) {return 0;}
TR_GlobalRegisterNumber getGlobalGPRFromHPR (TR_GlobalRegisterNumber n) {return 0;}

TR_GlobalRegisterNumber getFirstGlobalFPR() {return _lastGlobalGPR + 1;}
TR_GlobalRegisterNumber setFirstGlobalFPR(TR_GlobalRegisterNumber n) {return (_firstGlobalFPR = n);}
TR_GlobalRegisterNumber getLastGlobalFPR() {return _lastGlobalFPR;}
Expand All @@ -952,11 +943,7 @@ class OMR_EXTENSIBLE CodeGenerator

uint16_t getNumberOfGlobalRegisters();

#ifdef TR_HOST_S390
uint16_t getNumberOfGlobalGPRs();
#else
uint16_t getNumberOfGlobalGPRs() {return _lastGlobalGPR + 1;}
#endif
uint16_t getNumberOfGlobalFPRs() {return _lastGlobalFPR - _lastGlobalGPR;}
uint16_t getNumberOfGlobalVRFs() {return _lastGlobalVRF - _firstGlobalVRF;}

Expand All @@ -967,7 +954,6 @@ class OMR_EXTENSIBLE CodeGenerator
uint8_t setGlobalFPRPartitionLimit(uint8_t l) {return (_globalFPRPartitionLimit = l);}

bool isGlobalGPR(TR_GlobalRegisterNumber n) {return n <= _lastGlobalGPR;}
bool isGlobalHPR(TR_GlobalRegisterNumber n) {return (n >= _firstGlobalHPR && n <= _lastGlobalHPR);}

bool isAliasedGRN(TR_GlobalRegisterNumber n);
TR_GlobalRegisterNumber getOverlappedAliasForGRN(TR_GlobalRegisterNumber n);
Expand Down Expand Up @@ -1353,7 +1339,6 @@ class OMR_EXTENSIBLE CodeGenerator
bool isLiteralPoolOnDemandOn () { return false; }
bool supportsOnDemandLiteralPool() { return false; }
bool supportsDirectIntegralLoadStoresFromLiteralPool() { return false; }
bool supportsHighWordFacility() { return false; }

bool inlineDirectCall(TR::Node *node, TR::Register *&resultReg) { return false; }

Expand Down Expand Up @@ -1941,8 +1926,6 @@ class OMR_EXTENSIBLE CodeGenerator

TR_RegisterMask _liveRealRegisters[NumRegisterKinds];
TR_GlobalRegisterNumber _lastGlobalGPR;
TR_GlobalRegisterNumber _firstGlobalHPR;
TR_GlobalRegisterNumber _lastGlobalHPR;
TR_GlobalRegisterNumber _firstGlobalFPR;
TR_GlobalRegisterNumber _lastGlobalFPR;
TR_GlobalRegisterNumber _firstOverlappedGlobalFPR;
Expand Down
9 changes: 1 addition & 8 deletions compiler/codegen/OMRGCRegisterMap.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ class GCRegisterMap

TR_ALLOC(TR_Memory::GCRegisterMap)

GCRegisterMap() : _map(0), _registerSaveDescription(0), _hprmap(0) {}
GCRegisterMap() : _map(0), _registerSaveDescription(0) {}

TR::GCRegisterMap * self();

Expand All @@ -57,20 +57,13 @@ class GCRegisterMap
void maskRegistersWithInfoBits(uint32_t mask, uint32_t info) {_map = (mask & (_map | info));}
void setInfoBits(uint32_t info) {_map |= info;}

uint32_t getHPRMap() {return _hprmap;}
void setHighWordRegisterBits(uint32_t bits) {_hprmap |= bits;}
void resetHighWordRegisterBits(uint32_t bits) { _hprmap &= ~bits; }
void emptyHPR() {_hprmap = 0;}

uint32_t getRegisterSaveDescription() {return _registerSaveDescription;}
void setRegisterSaveDescription(uint32_t bits) {_registerSaveDescription = bits;}

private:

uint32_t _map;
uint32_t _registerSaveDescription;
uint32_t _hprmap;

};

}
Expand Down
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