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Test failure: JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out #60154

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VincentBu opened this issue Oct 8, 2021 · 32 comments · Fixed by #63357 or #64140
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arch-arm64 arch-x64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci Blocking PR or rolling runs of 'runtime' or 'runtime-extra-platforms' disabled-test The test is disabled in source code against the issue GCStress os-linux Linux OS (any supported distro) os-mac-os-x macOS aka OSX os-windows
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@VincentBu
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VincentBu commented Oct 8, 2021

Run: runtime-coreclr gcstress0x3-gcstress0xc 20211003.1
Failed test;

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open

- readytorun/coreroot_determinism/coreroot_determinism/coreroot_determinism.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/*

CoreCLR OSX arm64 Checked gcstress0x3 @ OSX.1100.ARM64.Open

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR windows arm64 Checked gcstress0x3 @ Windows.10.Arm64v8.Open

- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

One of error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 10/3/2021 2:59:49 PM, end: 10/3/2021 3:59:49 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 10/3/2021 2:59:53 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:15 PM
Beginning test case Abs.Double at 10/3/2021 3:00:15 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:23 PM
Beginning test case Abs.Int16 at 10/3/2021 3:00:23 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:27 PM
Beginning test case Abs.Int32 at 10/3/2021 3:00:27 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:33 PM
Beginning test case Abs.Int64 at 10/3/2021 3:00:33 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:39 PM
Beginning test case Abs.SByte at 10/3/2021 3:00:39 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:44 PM
Beginning test case Abs.Single at 10/3/2021 3:00:44 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenar


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()
Build Kind Start Time
1582767 Rolling 2022-31-01
1583845 Rolling 2022-01-02
1585006 Rolling 2022-01-02
1589146 Rolling 2022-03-02
1590573 Rolling 2022-03-02
@dotnet-issue-labeler dotnet-issue-labeler bot added area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI untriaged New issue has not been triaged by the area owner labels Oct 8, 2021
@ghost
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ghost commented Oct 8, 2021

Tagging subscribers to this area: @JulieLeeMSFT
See info in area-owners.md if you want to be subscribed.

Issue Details

Run: runtime-coreclr gcstress0x3-gcstress0xc 20211003.1
Failed test;

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open

- readytorun/coreroot_determinism/coreroot_determinism/coreroot_determinism.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/*

CoreCLR OSX arm64 Checked gcstress0x3 @ OSX.1100.ARM64.Open

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR windows arm64 Checked gcstress0x3 @ Windows.10.Arm64v8.Open

- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

One of error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 10/3/2021 2:59:49 PM, end: 10/3/2021 3:59:49 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 10/3/2021 2:59:53 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:15 PM
Beginning test case Abs.Double at 10/3/2021 3:00:15 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:23 PM
Beginning test case Abs.Int16 at 10/3/2021 3:00:23 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:27 PM
Beginning test case Abs.Int32 at 10/3/2021 3:00:27 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:33 PM
Beginning test case Abs.Int64 at 10/3/2021 3:00:33 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:39 PM
Beginning test case Abs.SByte at 10/3/2021 3:00:39 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/3/2021 3:00:44 PM
Beginning test case Abs.Single at 10/3/2021 3:00:44 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenar


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()
Author: VincentBu
Assignees: -
Labels:

arch-arm64, os-linux, os-mac-os-x, os-windows, GCStress, arch-x64, area-CodeGen-coreclr, untriaged

Milestone: -

@tannergooding
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This looks to be a simple timeout issue under GCStress. The test likely needs to be split apart like we did for some of the other scenarios.

@echesakov, you had some tool or infrastructure to help support splitting these IIRC?

@JulieLeeMSFT JulieLeeMSFT added this to the 7.0.0 milestone Oct 8, 2021
@JulieLeeMSFT JulieLeeMSFT removed the untriaged New issue has not been triaged by the area owner label Oct 8, 2021
@echesakov
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@echesakov, you had some tool or infrastructure to help support splitting these IIRC?

@tannergooding Correct, I stashed it here. We should probably resurrect and improve that work.

@VincentBu
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Failed again in: runtime-coreclr gcstress0x3-gcstress0xc 20211017.1

Failed test:


CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector256_1/Vector256_1_ro/Vector256_1_ro.sh
- JIT/HardwareIntrinsics/X86/Avx2/Avx2_ro/Avx2_ro.sh
- JIT/HardwareIntrinsics/X86/Sse2/Sse2_ro/Sse2_ro.sh
- JIT/HardwareIntrinsics/X86/Avx/Avx_ro/Avx_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR windows arm64 Checked gcstress0x3 @ Windows.10.Arm64v8.Open
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd

One of error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 10/17/2021 2:17:12 PM, end: 10/17/2021 3:17:12 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 10/17/2021 2:17:16 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:17:37 PM
Beginning test case Abs.Double at 10/17/2021 2:17:37 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:17:45 PM
Beginning test case Abs.Int16 at 10/17/2021 2:17:45 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:17:50 PM
Beginning test case Abs.Int32 at 10/17/2021 2:17:50 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:17:55 PM
Beginning test case Abs.Int64 at 10/17/2021 2:17:55 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:18:01 PM
Beginning test case Abs.SByte at 10/17/2021 2:18:01 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/17/2021 2:18:05 PM
Beginning test case Abs.Single at 10/17/2021 2:18:05 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunR


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@VincentBu
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Failed again in: runtime-coreclr r2r-extra 20211024.1

Failed test:

R2R Linux arm64 Checked gcstress0xf @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652

- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/X86/Avx2/Avx2_ro/Avx2_ro.sh
- JIT/HardwareIntrinsics/*

Error message:

rm: cannot remove 'IL-CG2/composite-r2r.dll': No such file or directory
/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh: line 246: -r:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/IL-CG2/*.dll: No such file or directory
rm: cannot remove '/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/TestLibrary.dll.rsp': No such file or directory
rm: cannot remove '/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.dll.rsp': No such file or directory

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh Timed Out (timeout in milliseconds: 5400000 from variable __TestTimeout, start: 10/25/2021 5:49:23 AM, end: 10/25/2021 7:19:23 AM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.output.txt
Raw output:
BEGIN EXECUTION
in takeLock
/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/IL-CG2/TestLibrary.dll
Response file: /root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/TestLibrary.dll.rsp
/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/IL-CG2/TestLibrary.dll
-o:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/TestLibrary.dll
-r:/root/helix/work/correlation/System..dll
-r:/root/helix/work/correlation/Microsoft..dll
-r:/root/helix/work/correlation/mscorlib.dll
--verify-type-and-field-layout
--targetarch:arm64
-O
Running CrossGen2:  dotnet /root/helix/work/correlation/crossgen2/crossgen2.dll @/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/TestLibrary.dll.rsp

Emitting R2R PE file: /root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/TestLibrary.dll
/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/IL-CG2/Vector256_r.dll
Response file: /root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.dll.rsp
/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/IL-CG2/Vector256_r.dll
-o:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.dll
-r:/root/helix/work/correlation/System..dll
-r:/root/helix/work/correlation/Microsoft..dll
-r:/root/helix/work/correlation/mscorlib.dll
--verify-type-and-field-layout
--targetarch:arm64
-O
Running CrossGen2:  dotnet /root/helix/work/correlation/crossgen2/crossgen2.dll @/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.dll.rsp

Emitting R2R PE file: /root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.dll
in ReleaseLock
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_r.dll ''
Beginning test case Abs.Byte at 10/25/2021 5:49:50 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 10/25/2021 5:50:10 AM
Beginning test case Abs.Double at 10/25/2021 5:50:10 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScena


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_r_Vector256_r_._General_Vector256_Vector256_r_Vector256_r_sh()

@VincentBu
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Contributor Author

Failed again in: runtime-coreclr gcstress0x3-gcstress0xc 20211107.2

Failed test:

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/X86/Avx2/Avx2_ro/Avx2_ro.sh
- JIT/HardwareIntrinsics/X86/Sse2/Sse2_ro/Sse2_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 11/7/2021 3:30:42 PM, end: 11/7/2021 4:30:42 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 11/7/2021 3:30:46 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:08 PM
Beginning test case Abs.Double at 11/7/2021 3:31:08 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:15 PM
Beginning test case Abs.Int16 at 11/7/2021 3:31:15 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:20 PM
Beginning test case Abs.Int32 at 11/7/2021 3:31:20 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:25 PM
Beginning test case Abs.Int64 at 11/7/2021 3:31:25 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:31 PM
Beginning test case Abs.SByte at 11/7/2021 3:31:31 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/7/2021 3:31:36 PM
Beginning test case Abs.Single at 11/7/2021 3:31:36 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenar


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@VincentBu
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Contributor Author

Failed again in: runtime-coreclr gcstress-extra 20211114.1

Failed test:

CoreCLR Linux arm Checked gcstress0xc_zapdisable_heapverify1 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
- JIT/HardwareIntrinsics/General/Vector64/Vector64_r/Vector64_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh

CoreCLR Linux arm Checked gcstress0xc_jitminopts_heapverify1 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector64/Vector64_r/Vector64_r.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

CoreCLR Linux arm64 Checked gcstress0xc_zapdisable_heapverify1 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

One of error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh Timed Out (timeout in milliseconds: 5400000 from variable __TestTimeout, start: 11/14/2021 10:51:05 PM, end: 11/15/2021 12:21:05 AM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_r.dll ''
Beginning test case Abs.Byte at 11/14/2021 10:51:33 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:52:23 PM
Beginning test case Abs.Double at 11/14/2021 10:52:23 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:52:40 PM
Beginning test case Abs.Int16 at 11/14/2021 10:52:40 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:52:50 PM
Beginning test case Abs.Int32 at 11/14/2021 10:52:50 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:52:59 PM
Beginning test case Abs.Int64 at 11/14/2021 10:52:59 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:53:11 PM
Beginning test case Abs.SByte at 11/14/2021 10:53:11 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/14/2021 10:53:20 PM
Beginning test case Abs.Single at 11/14/2021 10:53:20 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scen


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_r_Vector256_r_._General_Vector256_Vector256_r_Vector256_r_sh()

@VincentBu
Copy link
Contributor Author

Failed again in: runtime-coreclr gcstress0x3-gcstress0xc 20211124.1

Failed test:

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR OSX arm64 Checked gcstress0x3 @ OSX.1100.ARM64.Open
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- Loader/binding/tracing/BinderTracingTest.ResolutionFlow/BinderTracingTest.ResolutionFlow.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR OSX arm64 Checked gcstress0xc @ OSX.1100.ARM64.Open
- ilasm/PortablePdb/IlasmPortablePdbTests/IlasmPortablePdbTests.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector256_1/Vector256_1_ro/Vector256_1_ro.sh

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 11/24/2021 10:20:45 PM, end: 11/24/2021 11:20:45 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 11/24/2021 10:20:47 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:05 PM
Beginning test case Abs.Double at 11/24/2021 10:21:05 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:11 PM
Beginning test case Abs.Int16 at 11/24/2021 10:21:11 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:15 PM
Beginning test case Abs.Int32 at 11/24/2021 10:21:15 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:20 PM
Beginning test case Abs.Int64 at 11/24/2021 10:21:20 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:25 PM
Beginning test case Abs.SByte at 11/24/2021 10:21:25 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 11/24/2021 10:21:30 PM
Beginning test case Abs.Single at 11/24/2021 10:21:30 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@VincentBu
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Contributor Author

Failed again in: runtime-coreclr gcstress0x3-gcstress0xc 20211205.1

Failed test:

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 12/5/2021 2:38:25 PM, end: 12/5/2021 3:38:25 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 12/5/2021 2:38:28 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:38:44 PM
Beginning test case Abs.Double at 12/5/2021 2:38:44 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:38:50 PM
Beginning test case Abs.Int16 at 12/5/2021 2:38:50 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:38:55 PM
Beginning test case Abs.Int32 at 12/5/2021 2:38:55 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:38:59 PM
Beginning test case Abs.Int64 at 12/5/2021 2:38:59 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:39:04 PM
Beginning test case Abs.SByte at 12/5/2021 2:39:04 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/5/2021 2:39:09 PM
Beginning test case Abs.Single at 12/5/2021 2:39:09 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenar


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@VincentBu
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Contributor Author

Failed again in: runtime-coreclr gcstress-extra 20211212.1

Failed test:

CoreCLR Linux arm Checked gcstress0xc_zapdisable_heapverify1 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector64/Vector64_r/Vector64_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh

CoreCLR Linux arm Checked gcstress0xc_jitminopts_heapverify1 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector64/Vector64_r/Vector64_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 5400000 from variable __TestTimeout, start: 12/12/2021 10:58:37 PM, end: 12/13/2021 12:28:37 AM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 12/12/2021 10:58:43 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 10:59:26 PM
Beginning test case Abs.Double at 12/12/2021 10:59:26 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 10:59:41 PM
Beginning test case Abs.Int16 at 12/12/2021 10:59:41 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 10:59:47 PM
Beginning test case Abs.Int32 at 12/12/2021 10:59:47 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 10:59:54 PM
Beginning test case Abs.Int64 at 12/12/2021 10:59:54 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 11:00:02 PM
Beginning test case Abs.SByte at 12/12/2021 11:00:03 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/12/2021 11:00:09 PM
Beginning test case Abs.Single at 12/12/2021 11:00:09 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@BruceForstall
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@tannergooding @echesakovMSFT We continue to see lots of timeouts in these tests for gcstress / gcstress-extra, mostly (although apparently not exclusively) on Linux arm32. Should we just disable them for Linux arm32? Or for GCStress (until and if they are broken up)?

@echesakov
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@BruceForstall I think we should disable them for some of the scenarios. I will look into this.

@VincentBu
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Failde again in: runtime-coreclr gcstress0x3-gcstress0xc 20211226.1

Failed test:

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652

- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open

- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector256_1/Vector256_1_ro/Vector256_1_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440

- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 12/26/2021 3:00:37 PM, end: 12/26/2021 4:00:37 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 12/26/2021 3:00:40 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:00:57 PM
Beginning test case Abs.Double at 12/26/2021 3:00:57 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:01:04 PM
Beginning test case Abs.Int16 at 12/26/2021 3:01:04 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:01:09 PM
Beginning test case Abs.Int32 at 12/26/2021 3:01:09 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:01:14 PM
Beginning test case Abs.Int64 at 12/26/2021 3:01:14 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:01:20 PM
Beginning test case Abs.SByte at 12/26/2021 3:01:20 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 12/26/2021 3:01:25 PM
Beginning test case Abs.Single at 12/26/2021 3:01:25 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunR


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@VincentBu
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Failed again in: runtime-coreclr gcstress0x3-gcstress0xc 20220102.1

Failed test:

CoreCLR Linux arm64 Checked gcstress0x3 @ (Ubuntu.1804.Arm64.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm64v8-20210531091519-97d8652
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux arm Checked gcstress0x3 @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector64/Vector64_ro/Vector64_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh

CoreCLR Linux x64 Checked gcstress0x3 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh

CoreCLR Linux arm Checked gcstress0xc @ (Ubuntu.1804.Arm32.Open)Ubuntu.1804.Armarch.Open@mcr.microsoft.com/dotnet-buildtools/prereqs:ubuntu-18.04-helix-arm32v7-bfcd90a-20200121150440
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

Error message:

cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 3600000 from variable __TestTimeout, start: 1/2/2022 2:58:13 PM, end: 1/2/2022 3:58:13 PM)

Return code:      -100
Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false Vector256_ro.dll ''
Beginning test case Abs.Byte at 1/2/2022 2:58:16 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:58:33 PM
Beginning test case Abs.Double at 1/2/2022 2:58:33 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:58:39 PM
Beginning test case Abs.Int16 at 1/2/2022 2:58:39 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:58:45 PM
Beginning test case Abs.Int32 at 1/2/2022 2:58:45 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:58:50 PM
Beginning test case Abs.Int64 at 1/2/2022 2:58:50 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:58:56 PM
Beginning test case Abs.SByte at 1/2/2022 2:58:56 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/2/2022 2:59:01 PM
Beginning test case Abs.Single at 1/2/2022 2:59:01 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
B


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_sh()

@echesakov echesakov linked a pull request Jan 4, 2022 that will close this issue
@VincentBu
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Failed again in: runtime-coreclr jitstress-isas-x86 20220115.1

Failed test:

CoreCLR windows x86 Checked jitstress_isas_x86_nosse2 @ Windows.10.Amd64.Open
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_ro\\Vector128_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_ro\\Vector128_1_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_r\\Vector128_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_r\\Vector256_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_r\\Vector128_1_r.cmd

CoreCLR windows x86 Checked jitstress_isas_2_x86_nosse2 @ Windows.10.Amd64.Open
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_ro\\Vector128_1_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_r\\Vector256_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_r\\Vector128_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_r\\Vector128_1_r.cmd

CoreCLR windows x64 Checked jitstress_isas_1_x86_nosse2 @ Windows.10.Amd64.Open
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_ro\\Vector128_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_ro\\Vector128_1_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_r\\Vector256_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_r\\Vector128_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_r\\Vector128_1_r.cmd

CoreCLR windows x86 Checked jitstress_isas_1_x86_nosse2 @ Windows.10.Amd64.Open
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_ro\\Vector128_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_ro\\Vector128_1_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_r\\Vector256_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_r\\Vector128_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_r\\Vector128_1_r.cmd

CoreCLR windows x64 Checked jitstress_isas_2_x86_nosse2 @ Windows.10.Amd64.Open
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_ro\\Vector256_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_ro\\Vector128_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128_1\\Vector128_1_ro\\Vector128_1_ro.cmd
- JIT\\HardwareIntrinsics\\General\\Vector256\\Vector256_r\\Vector256_r.cmd
- JIT\\HardwareIntrinsics\\General\\Vector128\\Vector128_r\\Vector128_r.cmd

CoreCLR Linux x64 Checked jitstress_isas_x86_nosse2 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector128_1/Vector128_1_ro/Vector128_1_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_r/Vector128_r.sh

CoreCLR Linux x64 Checked jitstress_isas_2_x86_nosse2 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector128_1/Vector128_1_ro/Vector128_1_ro.sh
- JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh

CoreCLR Linux x64 Checked jitstress_isas_1_x86_nosse2 @ Ubuntu.1804.Amd64.Open
- JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh
- JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh
- JIT/HardwareIntrinsics/General/Vector128_1/Vector128_1_ro/Vector128_1_ro.sh

Error message:

Return code:      1
Raw output file:      C:\h\w\BD4109DC\w\AC0E09C5\uploads\Reports\JIT.HardwareIntrinsics\General\Vector256\Vector256_ro\Vector256_ro.output.txt
Raw output:
BEGIN EXECUTION
"C:\h\w\BD4109DC\p\corerun.exe" -p "System.Reflection.Metadata.MetadataUpdater.IsSupported=false"  Vector256_ro.dll
Beginning test case Abs.Byte at 1/16/2022 1:00:08 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:10 AM
Beginning test case Abs.Double at 1/16/2022 1:00:10 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:10 AM
Beginning test case Abs.Int16 at 1/16/2022 1:00:10 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:11 AM
Beginning test case Abs.Int32 at 1/16/2022 1:00:11 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:11 AM
Beginning test case Abs.Int64 at 1/16/2022 1:00:11 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:11 AM
Beginning test case Abs.SByte at 1/16/2022 1:00:11 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario

Ending test case at 1/16/2022 1:00:12 AM
Beginning test case Abs.Single at 1/16/2022 1:00:12 AM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunClsVarScenario
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassLclFldScenario
Begin


Stack trace
   at JIT_HardwareIntrinsics._General_Vector256_Vector256_ro_Vector256_ro_._General_Vector256_Vector256_ro_Vector256_ro_cmd()

@radical
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radical commented Jan 22, 2022

Hitting these failures https://dev.azure.com/dnceng/public/_build/results?buildId=1566046&view=logs&jobId=9eaa4d7e-225e-55b8-2a77-e1ac7e76d448&j=9eaa4d7e-225e-55b8-2a77-e1ac7e76d448&t=f70528f6-0b93-5c49-dfc7-de8b842ee9d6

     > /private/tmp/helix/working/C8700A47/w/B2D509DF/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
      Expected: True
      Actual:   False
      Stack Trace:
           at JIT_HardwareIntrinsics._General_Vector256_Vector256_r_Vector256_r_._General_Vector256_Vector256_r_Vector256_r_sh()
      Output:
        Fatal error. System.Runtime.InteropServices.SEHException (0x80004005): External component has thrown an exception.
           at JIT.HardwareIntrinsics.General.VectorBooleanBinaryOpTest__GreaterThanAllDouble.RunBasicScenario_UnsafeRead()
           at JIT.HardwareIntrinsics.General.Program.GreaterThanAllDouble()
           at JIT.HardwareIntrinsics.General.Program.Main(System.String[])
        task_for_pid(19874) FAILED 5 (os/kern) failure
        /private/tmp/helix/working/C8700A47/w/B2D509DF/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh: line 417: 19874 Abort trap: 6           (core dumped) $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"
> /private/tmp/helix/working/C8700A47/w/B2D509DF/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_r/Vector256_r.sh
    JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh [FAIL]
      Fatal error. System.Runtime.InteropServices.SEHException (0x80004005): External component has thrown an exception.
         at JIT.HardwareIntrinsics.General.VectorBooleanBinaryOpTest__GreaterThanAllDouble.RunBasicScenario_UnsafeRead()
         at JIT.HardwareIntrinsics.General.Program.GreaterThanAllDouble()
         at JIT.HardwareIntrinsics.General.Program.Main(System.String[])
      task_for_pid(19872) FAILED 5 (os/kern) failure
      /private/tmp/helix/working/C8700A47/w/B2D509DF/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh: line 417: 19872 Abort trap: 6           (core dumped) $LAUNCHER $ExePath "${CLRTestExecutionArguments[@]}"

@ghost ghost removed the in-pr There is an active PR which will close this issue when it is merged label Jan 24, 2022
@tannergooding
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#64140 won't have fixed the GCStress timeout issue which was a different issue from what got piled on here at the end.

@sbomer
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sbomer commented Feb 1, 2022

We hit a timeout again on the rolling build. Good news is it's only for one testcase, Vector256_ro.sh. https://runfo.azurewebsites.net/view/build/?number=1582767. Is anyone looking into addressing the timeout failures?

JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh [FAIL]
      
      cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out (timeout in milliseconds: 600000 from variable __TestTimeout, start: 1/31/2022 9:36:31 PM, end: 1/31/2022 9:46:31 PM)

Could we keep this issue about the timeout and file new issues for different failures, even if it happens to be the same testcase? @VincentBu I hope you don't mind; I went ahead and moved your last comment to a new issue: #64587

@sbomer sbomer changed the title Test failure JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Test failure: JIT/HardwareIntrinsics/General/Vector256/Vector256_ro/Vector256_ro.sh Timed Out Feb 1, 2022
@tannergooding
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Is anyone looking into addressing the timeout failures?

This is something that is simply due to the number of tests that exist due to the number of hardware intrinsics that exist. This should get resolved as part of the general test cleanup changes (that I believe @trylek is working on).

We could potentially split this explicitly into two projects in the interim, but I think that's the best we could do for now.

@sbomer
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sbomer commented Feb 1, 2022

This is starting to repro more consistently - it caused the last two rolling builds to fail and is showing up in lots of PR runs: https://runfo.azurewebsites.net/search/tests/?q=started%3A~7%20definition%3Aruntime%20name%3A%22jit%2Fhardwareintrinsics%2Fgeneral%2Fvector256%2Fvector256_ro%2Fvector256_ro.sh%22

Could we bump the priority on fixing this, or disable the testcase?

@echesakov
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echesakov commented Feb 1, 2022

Hi @sbomer, let me work on #63357 tonight/tomorrow - this will disable the "non-relevant tests" on platforms where such intrinsics are not supported. This is not an ideal solution (since we still want to do test NotSupportedPlatform behaviour) but I don't see how else we can fix the timeout issue.

@sbomer
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sbomer commented Feb 1, 2022

Thanks @echesakovMSFT - so the failure is actually due to the intrinsics being unsupported on ARM? Do we know why they are timing out? It would be great if we could get at least Vector256_ro disabled tonight before the next rolling build, even if the others take longer to fix.

edit: I opened #64653 to selectively disable that test. Let me know if you prefer to take that or #63357.

@echesakov
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My guess is that each intrinsic call throws NotSupportedPlatformException and given that these are Arm32 (i.e. slow devices) - it takes a while to handle thousands of such calls.

@sbomer sbomer added the disabled-test The test is disabled in source code against the issue label Feb 2, 2022
@radical
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radical commented Feb 3, 2022

JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh failed again - Build, and log

    JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh [FAIL]
    cmdLine:/root/helix/work/workitem/e/JIT/HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.sh Timed Out (timeout in milliseconds: 600000 from variable __TestTimeout, start: 2/3/2022 5:42:29 AM, end: 2/3/2022 5:52:29 AM)
      
      Return code:      -100
      Raw output file:      /root/helix/work/workitem/uploads/Reports/JIT.HardwareIntrinsics/General/Vector128/Vector128_ro/Vector128_ro.output.txt

echesakov added a commit that referenced this issue Feb 3, 2022
Disable intrinsics tests that throw NotSupportedPlatformException on the corresponding platforms:

* Add JIT/HardwareIntrinsics/** to ExcludeList on Arm32 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/General/Vector256/** to ExcludeList on Arm64 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/X86/** to ExcludeList on Arm64 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/General/Vector64/** to ExcludeList on X64 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/Arm/** to ExcludeList on X64 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/General/Vector64/** to ExcludeList on X86 in src/tests/issues.targets

* Add JIT/HardwareIntrinsics/Arm/** to ExcludeList on X86 in src/tests/issues.targets
@ghost ghost locked as resolved and limited conversation to collaborators Mar 6, 2022
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arch-arm64 arch-x64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci Blocking PR or rolling runs of 'runtime' or 'runtime-extra-platforms' disabled-test The test is disabled in source code against the issue GCStress os-linux Linux OS (any supported distro) os-mac-os-x macOS aka OSX os-windows
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