Remove ZMM_RECOMMENDED_THRESHOLD workaround (#86552)

dotnet · May 21, 2023 · 37c2751 · 37c2751
1 parent 6fd4019
commit 37c2751
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Showing 4 changed files with 3 additions and 28 deletions.
diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp
@@ -2572,12 +2572,7 @@ void CodeGen::genCodeForMemmove(GenTreeBlk* tree)
     regNumber src  = genConsumeReg(srcIndir->Addr());
     unsigned  size = tree->Size();
 
-    unsigned simdSize = compiler->roundDownSIMDSize(size);
-    if (size <= ZMM_RECOMMENDED_THRESHOLD)
-    {
-        // Only use ZMM for large data due to possible CPU throttle issues
-        simdSize = min(YMM_REGSIZE_BYTES, simdSize);
-    }
+    const unsigned simdSize = compiler->roundDownSIMDSize(size);
     if ((size >= simdSize) && (simdSize > 0))
     {
         // Number of SIMD regs needed to save the whole src to regs.
@@ -3150,12 +3145,7 @@ void CodeGen::genCodeForInitBlkUnroll(GenTreeBlk* node)
     {
         regNumber srcXmmReg = node->GetSingleTempReg(RBM_ALLFLOAT);
         unsigned  regSize   = compiler->roundDownSIMDSize(size);
-        if (size < ZMM_RECOMMENDED_THRESHOLD)
-        {
-            // Involve ZMM only for large data due to possible downclocking.
-            regSize = min(regSize, YMM_REGSIZE_BYTES);
-        }
-        var_types loadType = compiler->getSIMDTypeForSize(regSize);
+        var_types loadType  = compiler->getSIMDTypeForSize(regSize);
         simd_t    vecCon;
         memset(&vecCon, (uint8_t)src->AsIntCon()->IconValue(), sizeof(simd_t));
         genSetRegToConst(srcXmmReg, loadType, &vecCon);
@@ -3413,11 +3403,6 @@ void CodeGen::genCodeForCpBlkUnroll(GenTreeBlk* node)
 
         // Get the largest SIMD register available if the size is large enough
         unsigned regSize = compiler->roundDownSIMDSize(size);
-        if (size < ZMM_RECOMMENDED_THRESHOLD)
-        {
-            // Involve ZMM only for large data due to possible downclocking.
-            regSize = min(regSize, YMM_REGSIZE_BYTES);
-        }
 
         auto emitSimdMovs = [&]() {
             if (srcLclNum != BAD_VAR_NUM)

diff --git a/src/coreclr/jit/lsraxarch.cpp b/src/coreclr/jit/lsraxarch.cpp
@@ -1488,13 +1488,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
                 // Lowering was expected to get rid of memmove in case of zero
                 assert(size > 0);
 
-                unsigned simdSize = compiler->roundDownSIMDSize(size);
-                if (size <= ZMM_RECOMMENDED_THRESHOLD)
-                {
-                    // Only use ZMM for large data due to possible CPU throttle issues
-                    simdSize = min(YMM_REGSIZE_BYTES, compiler->roundDownSIMDSize(size));
-                }
-
+                const unsigned simdSize = compiler->roundDownSIMDSize(size);
                 if ((size >= simdSize) && (simdSize > 0))
                 {
                     unsigned simdRegs = size / simdSize;

diff --git a/src/coreclr/jit/targetamd64.h b/src/coreclr/jit/targetamd64.h
@@ -112,8 +112,6 @@
   #define STACK_ALIGN              16      // stack alignment requirement
   #define STACK_ALIGN_SHIFT        4       // Shift-right amount to convert size in bytes to size in STACK_ALIGN units == log2(STACK_ALIGN)
 
-  #define ZMM_RECOMMENDED_THRESHOLD 128    // A general recommendation to use ZMM for data starting from this size in bytes
-
 #if ETW_EBP_FRAMED
   #define RBM_ETW_FRAMED_EBP        RBM_NONE
   #define RBM_ETW_FRAMED_EBP_LIST

diff --git a/src/coreclr/jit/targetx86.h b/src/coreclr/jit/targetx86.h
@@ -116,8 +116,6 @@
   #define YMM_REGSIZE_BYTES        32      // YMM register size in bytes
   #define ZMM_REGSIZE_BYTES        64      // ZMM register size in bytes
 
-  #define ZMM_RECOMMENDED_THRESHOLD 128    // A general recommendation to use ZMM for data starting from this size in bytes
-
   #define REGNUM_BITS              6       // number of bits in a REG_*
 
   #define REGSIZE_BYTES            4       // number of bytes in one register