Ok we're in a good state now

daquintero · Oct 19, 2024 · f5c84d6 · f5c84d6
1 parent ae5492a
commit f5c84d6
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Showing 4 changed files with 33 additions and 33 deletions.
diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py b/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py
@@ -538,21 +538,19 @@ def create_switch_fabric():
 
 # ## 3b. Digital Chip Implementation
 
-component = piel.flows.get_latest_digital_run_component(
+component = piel.flows.layout_truth_table(
+    truth_table=truth_table,
     module=full_flow_demo,
 )
-component.plot()
 
-component = piel.flows.layout_truth_table(
-    truth_table=truth_table,
+component = piel.flows.get_latest_digital_run_component(
     module=full_flow_demo,
 )
+component.plot()
 
 print("Truth Table Layout")
 component
 
-# ### 4a.
-
 # ## 4a. Driver-Amplfier Modelling
 
 # Now we will create a amplifier model using `sky130` components.

diff --git a/...full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v b/...full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v
@@ -4,49 +4,49 @@
 (* generator = "Amaranth" *)
 module top(bit_phase_0, bit_phase_1, input_fock_state_str);
   reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
-  (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_0;
   reg [4:0] bit_phase_0;
-  (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_1;
   reg [4:0] bit_phase_1;
-  (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
+  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
   input [2:0] input_fock_state_str;
   wire [2:0] input_fock_state_str;
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_0 = 5'h1f;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_0 = 5'h00;
     endcase
   end
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_1 = 5'h1f;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_1 = 5'h00;
     endcase

diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v
@@ -4,49 +4,49 @@
 (* generator = "Amaranth" *)
 module top(bit_phase_0, bit_phase_1, input_fock_state_str);
   reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
-  (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_0;
   reg [4:0] bit_phase_0;
-  (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_1;
   reg [4:0] bit_phase_1;
-  (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
+  (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
   input [2:0] input_fock_state_str;
   wire [2:0] input_fock_state_str;
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_0 = 5'h1f;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_0 = 5'h00;
     endcase
   end
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_1 = 5'h1f;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_1 = 5'h00;
     endcase

diff --git a/piel/file_system.py b/piel/file_system.py
@@ -709,7 +709,9 @@ def verify_install_file(install_file_path: pathlib.Path):
             output_path = pathlib.Path(input_path.__file__) / ".."
         except Exception:
             # TODO FIX this hacked af
-            output_path = pathlib.Path(input_path.__path__[0])
+            output_path_raw = pathlib.Path(input_path.__path__[0])
+            output_directory_name = output_path_raw.name
+            output_path = output_path_raw / output_directory_name
             pass
     elif isinstance(input_path, os.PathLike):
         output_path = pathlib.Path(input_path)