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Qiskit gates not qelib1.inc are now defined when dumped (Qiskit#9777)
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* non-standard gates

* Qiskit gates not qelib1.inc are now defined when dumped

---------

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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1ucian0 and mergify[bot] committed Mar 10, 2023
1 parent 5ce80ab commit 5a62949
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3 changes: 0 additions & 3 deletions qiskit/circuit/quantumcircuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -1623,7 +1623,6 @@ def qasm(
"sx",
"sxdg",
"cz",
"ccz",
"cy",
"swap",
"ch",
Expand All @@ -1636,8 +1635,6 @@ def qasm(
"cp",
"cu3",
"csx",
"cs",
"csdg",
"cu",
"rxx",
"rzz",
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8 changes: 8 additions & 0 deletions releasenotes/notes/fix_9559-ec05304e52ff841f.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
---
fixes:
- |
The Qiskit gates :class:`~.CCZGate`, :class:`~.CSGate`, :class:`~.CSdgGate` are not defined in
``qelib1.inc`` and, therefore, when dump as OpenQASM 2.0, their definition should be inserted in the file.
Fixes `#9559 <https://github.com/Qiskit/qiskit-terra/issues/9559>`__,
`#9721 <https://github.com/Qiskit/qiskit-terra/issues/9721>`__, and
`#9722 <https://github.com/Qiskit/qiskit-terra/issues/9722>`__.
62 changes: 58 additions & 4 deletions test/python/circuit/test_circuit_qasm.py
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
# copyright notice, and modified files need to carry a notice indicating
# that they have been altered from the originals.

"""Test Qiskit's QuantumCircuit class."""
"""Test Qiskit's gates in QASM2."""

import unittest
from math import pi
Expand All @@ -19,15 +19,15 @@
from qiskit import QuantumRegister, ClassicalRegister, QuantumCircuit
from qiskit.test import QiskitTestCase
from qiskit.circuit import Parameter, Qubit, Clbit, Gate
from qiskit.circuit.library import C3SXGate
from qiskit.circuit.library import C3SXGate, CCZGate, CSGate, CSdgGate, RZXGate
from qiskit.qasm.exceptions import QasmError

# Regex pattern to match valid OpenQASM identifiers
VALID_QASM2_IDENTIFIER = re.compile("[a-z][a-zA-Z_0-9]*")


class TestCircuitQasm(QiskitTestCase):
"""QuantumCircuit Qasm tests."""
"""QuantumCircuit QASM2 tests."""

def test_circuit_qasm(self):
"""Test circuit qasm() method."""
Expand Down Expand Up @@ -249,7 +249,9 @@ def test_circuit_qasm_with_composite_circuit_with_many_params_and_qubits(self):
self.assertEqual(original_str, qc.qasm())

def test_c3sxgate_roundtrips(self):
"""Test that C3SXGate correctly round trips. Qiskit gives this gate a different name
"""Test that C3SXGate correctly round trips.
Qiskit gives this gate a different name
('c3sx') to the name in Qiskit's version of qelib1.inc ('c3sqrtx') gate, which can lead to
resolution issues."""
qc = QuantumCircuit(4)
Expand All @@ -264,6 +266,58 @@ def test_c3sxgate_roundtrips(self):
parsed = QuantumCircuit.from_qasm_str(qasm)
self.assertIsInstance(parsed.data[0].operation, C3SXGate)

def test_cczgate_qasm(self):
"""Test that CCZ dumps definition as a non-qelib1 gate."""
qc = QuantumCircuit(3)
qc.append(CCZGate(), qc.qubits, [])
qasm = qc.qasm()
expected = """OPENQASM 2.0;
include "qelib1.inc";
gate ccz q0,q1,q2 { h q2; ccx q0,q1,q2; h q2; }
qreg q[3];
ccz q[0],q[1],q[2];
"""
self.assertEqual(qasm, expected)

def test_csgate_qasm(self):
"""Test that CS dumps definition as a non-qelib1 gate."""
qc = QuantumCircuit(2)
qc.append(CSGate(), qc.qubits, [])
qasm = qc.qasm()
expected = """OPENQASM 2.0;
include "qelib1.inc";
gate cs q0,q1 { p(pi/4) q0; cx q0,q1; p(-pi/4) q1; cx q0,q1; p(pi/4) q1; }
qreg q[2];
cs q[0],q[1];
"""
self.assertEqual(qasm, expected)

def test_csdggate_qasm(self):
"""Test that CSdg dumps definition as a non-qelib1 gate."""
qc = QuantumCircuit(2)
qc.append(CSdgGate(), qc.qubits, [])
qasm = qc.qasm()
expected = """OPENQASM 2.0;
include "qelib1.inc";
gate csdg q0,q1 { p(-pi/4) q0; cx q0,q1; p(pi/4) q1; cx q0,q1; p(-pi/4) q1; }
qreg q[2];
csdg q[0],q[1];
"""
self.assertEqual(qasm, expected)

def test_rzxgate_qasm(self):
"""Test that RZX dumps definition as a non-qelib1 gate."""
qc = QuantumCircuit(2)
qc.append(RZXGate(0), qc.qubits, [])
qasm = qc.qasm()
expected = """OPENQASM 2.0;
include "qelib1.inc";
gate rzx(param0) q0,q1 { h q1; cx q0,q1; rz(0) q1; cx q0,q1; h q1; }
qreg q[2];
rzx(0) q[0],q[1];
"""
self.assertEqual(qasm, expected)

def test_unbound_circuit_raises(self):
"""Test circuits with unbound parameters raises."""
qc = QuantumCircuit(1)
Expand Down

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