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fix misra violations
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@robbederks
robbederks committed Dec 13, 2022
1 parent 238b335 commit b53f2ef
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Showing 3 changed files with 76 additions and 57 deletions.
24 changes: 16 additions & 8 deletions board/drivers/fake_siren.h
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Original file line number Diff line number Diff line change
Expand Up @@ -8,16 +8,24 @@ bool fake_siren_enabled = false;

void fake_siren_codec_enable(bool enabled) {
if(enabled) {
i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x2B, (1U << 1)); // Left speaker mix from INA1
i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x2C, (1U << 1)); // Right speaker mix from INA1
i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x3D, 0x1F, 0b11111); // Left speaker volume
i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x3E, 0x1F, 0b11111); // Right speaker volume
i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x37, 0b101, 0b111); // INA gain
i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x4C, (1U << 7)); // Enable INA
i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x51, (1U << 7)); // Disable global shutdown
bool success = false;
success &= i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x2B, (1U << 1)); // Left speaker mix from INA1
success &= i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x2C, (1U << 1)); // Right speaker mix from INA1
success &= i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x3D, 0x1F, 0b11111); // Left speaker volume
success &= i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x3E, 0x1F, 0b11111); // Right speaker volume
success &= i2c_set_reg_mask(I2C5, CODEC_I2C_ADDR, 0x37, 0b101, 0b111); // INA gain
success &= i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x4C, (1U << 7)); // Enable INA
success &= i2c_set_reg_bits(I2C5, CODEC_I2C_ADDR, 0x51, (1U << 7)); // Disable global shutdown
if (!success) {
print("Failed to setup the codec for fake siren\n");
}
} else {
// Disable INA input. Make sure to retry a few times if the I2C bus is busy.
for(uint8_t i=0U; i<10U && !i2c_clear_reg_bits(I2C5, CODEC_I2C_ADDR, 0x4C, (1U << 7)); i++);
for(uint8_t i=0U; i<10U; i++) {
if (i2c_clear_reg_bits(I2C5, CODEC_I2C_ADDR, 0x4C, (1U << 7))) {
break;
}
}
}
}

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28 changes: 13 additions & 15 deletions board/stm32h7/lldac.h
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Original file line number Diff line number Diff line change
@@ -1,42 +1,40 @@


void dac_init(DAC_TypeDef *DAC, uint8_t channel, bool dma) {
register_set(&DAC->CR, 0U, 0xFFFFU);
register_set(&DAC->MCR, 0U, 0xFFFFU);
void dac_init(DAC_TypeDef *dac, uint8_t channel, bool dma) {
register_set(&dac->CR, 0U, 0xFFFFU);
register_set(&dac->MCR, 0U, 0xFFFFU);

switch(channel) {
case 1:
if (dma) {
register_set_bits(&DAC->CR, DAC_CR_DMAEN1);
register_set_bits(&dac->CR, DAC_CR_DMAEN1);
// register_set(&DAC->CR, (6U << DAC_CR_TSEL1_Pos), DAC_CR_TSEL1);
register_set_bits(&DAC->CR, DAC_CR_TEN1);
register_set_bits(&dac->CR, DAC_CR_TEN1);
} else {
register_clear_bits(&DAC->CR, DAC_CR_DMAEN1);
register_clear_bits(&dac->CR, DAC_CR_DMAEN1);
}
register_set_bits(&DAC->CR, DAC_CR_EN1);
register_set_bits(&dac->CR, DAC_CR_EN1);
break;
case 2:
if (dma) {
register_set_bits(&DAC->CR, DAC_CR_DMAEN2);
register_set_bits(&dac->CR, DAC_CR_DMAEN2);
} else {
register_clear_bits(&DAC->CR, DAC_CR_DMAEN2);
register_clear_bits(&dac->CR, DAC_CR_DMAEN2);
}
register_set_bits(&DAC->CR, DAC_CR_EN2);
register_set_bits(&dac->CR, DAC_CR_EN2);
break;
default:
break;
}
}

// Set channel 1 value, in mV
void dac_set(DAC_TypeDef *DAC, uint8_t channel, uint32_t value) {
void dac_set(DAC_TypeDef *dac, uint8_t channel, uint32_t value) {
uint32_t raw_val = MAX(MIN(value * (1U << 8U) / 3300U, (1U << 8U)), 0U);
switch(channel) {
case 1:
register_set(&DAC->DHR8R1, raw_val, 0xFFU);
register_set(&dac->DHR8R1, raw_val, 0xFFU);
break;
case 2:
register_set(&DAC->DHR8R2, raw_val, 0xFFU);
register_set(&dac->DHR8R2, raw_val, 0xFFU);
break;
default:
break;
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81 changes: 47 additions & 34 deletions board/stm32h7/lli2c.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@
// if we want it to be more async, we should use interrupts

#define I2C_TIMEOUT_US 100000U

// cppcheck-suppress misra-c2012-2.7; not sure why it triggers here?
bool i2c_status_wait(volatile uint32_t *reg, uint32_t mask, uint32_t val) {
uint32_t start_time = microsecond_timer_get();
while(((*reg & mask) != val) && (get_ts_elapsed(microsecond_timer_get(), start_time) < I2C_TIMEOUT_US));
Expand All @@ -11,7 +13,7 @@ bool i2c_status_wait(volatile uint32_t *reg, uint32_t mask, uint32_t val) {

bool i2c_write_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t value) {
// Setup transfer and send START + addr
bool start_success = false;
bool ret = false;
for(uint32_t i=0U; i<10U; i++) {
register_clear_bits(&I2C->CR2, I2C_CR2_ADD10);
I2C->CR2 = ((addr << 1U) & I2C_CR2_SADD_Msk);
Expand All @@ -28,32 +30,35 @@ bool i2c_write_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t value) {
if ((I2C->ISR & I2C_ISR_ARLO) != 0U) {
register_set_bits(&I2C->ICR, I2C_ICR_ARLOCF);
} else {
start_success = true;
ret = true;
break;
}
}

if (!start_success) {
return false;
if (!ret) {
goto end;
}

// Send data
if(!i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS)) {
return false;
ret = i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS);
if(!ret) {
goto end;
}
I2C->TXDR = reg;

if(!i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS)) {
return false;
ret = i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS);
if(!ret) {
goto end;
}
I2C->TXDR = value;

return true;
end:
return ret;
}

bool i2c_read_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t *value) {
// Setup transfer and send START + addr
bool start_success = false;
bool ret = false;
for(uint32_t i=0U; i<10U; i++) {
register_clear_bits(&I2C->CR2, I2C_CR2_ADD10);
I2C->CR2 = ((addr << 1U) & I2C_CR2_SADD_Msk);
Expand All @@ -70,67 +75,75 @@ bool i2c_read_reg(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t *value) {
if ((I2C->ISR & I2C_ISR_ARLO) != 0U) {
register_set_bits(&I2C->ICR, I2C_ICR_ARLOCF);
} else {
start_success = true;
ret = true;
break;
}
}

if (!start_success) {
return false;
if (!ret) {
goto end;
}

// Send data
if(!i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS)) {
return false;
ret = i2c_status_wait(&I2C->ISR, I2C_ISR_TXIS, I2C_ISR_TXIS);
if(!ret) {
goto end;
}
I2C->TXDR = reg;

// Restart
I2C->CR2 = (((addr << 1U) | 0x1) & I2C_CR2_SADD_Msk) | (1 << I2C_CR2_NBYTES_Pos) | I2C_CR2_RD_WRN | I2C_CR2_START;
if(!i2c_status_wait(&I2C->CR2, I2C_CR2_START, 0U)) {
return false;
I2C->CR2 = (((addr << 1) | 0x1U) & I2C_CR2_SADD_Msk) | (1U << I2C_CR2_NBYTES_Pos) | I2C_CR2_RD_WRN | I2C_CR2_START;
ret = i2c_status_wait(&I2C->CR2, I2C_CR2_START, 0U);
if(!ret) {
goto end;
}

// check if we lost arbitration
if ((I2C->ISR & I2C_ISR_ARLO) != 0U) {
register_set_bits(&I2C->ICR, I2C_ICR_ARLOCF);
return false;
ret = false;
goto end;
}

// Read data
if(!i2c_status_wait(&I2C->ISR, I2C_ISR_RXNE, I2C_ISR_RXNE)) {
return false;
ret = i2c_status_wait(&I2C->ISR, I2C_ISR_RXNE, I2C_ISR_RXNE);
if(!ret) {
goto end;
}
*value = I2C->RXDR;

// Stop
I2C->CR2 |= I2C_CR2_STOP;

return true;
end:
return ret;
}

bool i2c_set_reg_bits(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t bits) {
uint8_t value;
if(!i2c_read_reg(I2C, addr, reg, &value)) {
return false;
}
return i2c_write_reg(I2C, addr, reg, value | bits);
bool ret = i2c_read_reg(I2C, addr, reg, &value);
if(ret) {
ret = i2c_write_reg(I2C, addr, reg, value | bits);
}
return ret;
}

bool i2c_clear_reg_bits(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t bits) {
uint8_t value;
if(!i2c_read_reg(I2C, addr, reg, &value)) {
return false;
}
return i2c_write_reg(I2C, addr, reg, value & ~bits);
bool ret = i2c_read_reg(I2C, addr, reg, &value);
if(ret) {
ret = i2c_write_reg(I2C, addr, reg, value & (uint8_t) (~bits));
}
return ret;
}

bool i2c_set_reg_mask(I2C_TypeDef *I2C, uint8_t addr, uint8_t reg, uint8_t value, uint8_t mask) {
uint8_t old_value;
if(!i2c_read_reg(I2C, addr, reg, &old_value)) {
return false;
}
return i2c_write_reg(I2C, addr, reg, (old_value & ~mask) | (value & mask));
bool ret = i2c_read_reg(I2C, addr, reg, &old_value);
if(ret) {
ret = i2c_write_reg(I2C, addr, reg, (old_value & (uint8_t) (~mask)) | (value & mask));
}
return ret;
}

void i2c_init(I2C_TypeDef *I2C) {
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