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FW synch 12_0_0_pre4 #220

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Mar 4, 2022
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1f6e6ff
Updated URLs.
aehart Jan 7, 2022
214fffb
Removed ugly hack.
aehart Jan 7, 2022
4d49215
Updated list of working modules.
aehart Jan 7, 2022
4a2d7d1
Updated README.
aehart Jan 7, 2022
349e727
Execute everything in 2021 due to Y2K22 bug.
aehart Jan 7, 2022
8f148e8
Define separate getters for Z (signed) and R (unsigned).
aehart Jan 10, 2022
7d5f374
Fixed some comparisons to exactly match emulation.
aehart Jan 10, 2022
f3550c7
Use specific R/Z getters.
aehart Jan 10, 2022
42f58b2
Minor tweaks for agreement with emulation.
aehart Jan 10, 2022
cc3b8fb
Removed options that do not work with faketime.
aehart Jan 11, 2022
9aadbc7
Removed faketime.
aehart Jan 11, 2022
7c72cbe
Reverted to version on master branch.
aehart Jan 17, 2022
66c1ed0
Enabled testing all barrel-only TCs.
aehart Jan 17, 2022
e8bd6ab
Updated to fw_synch_220119.
aehart Jan 19, 2022
861bd5b
removed the missing 0x DTC Link bodge, and fixed the FileReaderFIFO t…
meisonlikesicecream Jan 20, 2022
245fc45
fixed compare script issue with binned memories now having 0x at the …
meisonlikesicecream Jan 20, 2022
dfb9546
added some awk magic to avoid vivado incorrectly letting errors go un…
meisonlikesicecream Jan 20, 2022
6d40d39
Require "error" to be at the beginning of a line.
aehart Jan 21, 2022
06c75cf
Updated to fw_synch_220202.
aehart Feb 3, 2022
2cddc0e
Synced some comparisons.
aehart Feb 7, 2022
3415d04
Synced some comparisons.
aehart Feb 7, 2022
22f7c73
Updated reduced config test vectors.
aehart Feb 8, 2022
cd0aa9f
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
5f438d8
New test vectors
Feb 1, 2022
8ccd22f
Fixes for z match range
Feb 1, 2022
114c4e4
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
aee412d
Fix MatchCalculator to match changes in emulation
Feb 1, 2022
e0ed57c
Some cleanup of comment and commented out code
Feb 1, 2022
c3752c3
All modules fully match (exporting MP_L3PHIC)
bryates Feb 2, 2022
6710c31
Update workflow for automatic builds
Feb 4, 2022
c45d215
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
c93178e
New test vectors
Feb 1, 2022
f7d8eb4
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
2408c52
Some cleanup of comment and commented out code
Feb 1, 2022
c243028
All modules fully match (exporting MP_L3PHIC)
bryates Feb 2, 2022
29c9d65
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
3241522
New test vectors
Feb 1, 2022
cd846c7
Process 100 events
Feb 1, 2022
36898f5
Some cleanup of comment and commented out code
Feb 1, 2022
f14ac15
All modules fully match (exporting MP_L3PHIC)
bryates Feb 2, 2022
0f07b12
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
42cee03
New test vectors
Feb 1, 2022
3bd774d
Various hacks to try to bring timing down fow MP module
Jan 31, 2022
639f37e
Some cleanup of comment and commented out code
Feb 1, 2022
1b21c76
All modules fully match (exporting MP_L3PHIC)
bryates Feb 2, 2022
5973b27
Update GitLab_CI.yml
bryates Feb 5, 2022
ab58c36
Copied URLs from MP_Ryd_Test_rebase.
aehart Feb 7, 2022
58ad214
Added MP_Ryd_Test_rebase_sync.
aehart Feb 7, 2022
4fd9806
Some cleanup of unused variable and renaming
Feb 8, 2022
cdce69f
Further cleanup of code, renaming variables and removing unused code
Feb 8, 2022
e5944ec
../TrackletAlgorithm/MatchEngineUnit.h
Feb 11, 2022
dcfab5b
Cleanup of the MP code
Feb 11, 2022
75b6f6a
Fix writing of full matches
Feb 14, 2022
9650183
Updated test vectors.
aehart Feb 14, 2022
b79eceb
Removed testing branches.
aehart Feb 14, 2022
10f1e5b
Fixed URLs for reduced config.
aehart Feb 14, 2022
c1875e9
Copied URLs from MP_Ryd_Test_rebase.
aehart Feb 7, 2022
3a9ef37
Fixes for checking valid_L3
Feb 15, 2022
b62664b
Minor cleanup and adjustments
bryates Feb 15, 2022
6bbccbd
Added all MC and MP barrel layers to `download.sh`
bryates Feb 17, 2022
9112da0
Updated test data to fw_synch_220217 tag.
aehart Feb 18, 2022
4e4b935
Fixed typo in comment
bryates Feb 18, 2022
f1a2dc6
Updated to fw_synch_220220 test vectors.
aehart Feb 21, 2022
6e3c346
For binned memories, read extra characters of hex prefix.
aehart Feb 21, 2022
587734b
Removed unnecessary allow_failure.
aehart Feb 21, 2022
213d703
Removed commented code
bryates Feb 21, 2022
e9d255c
Updated recipe for generating test vectors.
aehart Feb 22, 2022
1c0c52a
Named iphi_ size
bryates Feb 28, 2022
5827ad0
Z bin no flag
bryates Feb 28, 2022
7086cb6
Using auto
bryates Feb 28, 2022
4528183
Removed `nonzero`
bryates Feb 28, 2022
c840629
proj/stub fine phi constants (include 2S)
bryates Feb 28, 2022
ab426f1
`istub_ == 0`
bryates Feb 28, 2022
4979ad1
detectorshift
bryates Mar 1, 2022
02ce3b1
Using auto
bryates Mar 1, 2022
6195026
Named constants
bryates Mar 1, 2022
26120cf
Removed unused function.
aehart Mar 1, 2022
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9 changes: 3 additions & 6 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -66,8 +66,8 @@ stages: # ---------------------------------------------------------------------
- cd IntegrationTests/${PROJ_NAME}/script
- pwd; ls -la; #debug
- vivado_hls -f ./compileHLS.tcl
- vivado -mode batch -source ./makeProject.tcl
- vivado -mode batch -source ./runSim.tcl
- vivado -mode batch -source ./makeProject.tcl | awk 'BEGIN{IGNORECASE=1} /^error/ {exit_code=1;} // {print $0;} END{exit exit_code}'
- vivado -mode batch -source ./runSim.tcl | awk 'BEGIN{IGNORECASE=1} /^error/ {exit_code=1;} // {print $0;} END{exit exit_code}'
artifacts:
when: on_success
name: "$CI_JOB_NAME-$CI_JOB_STAGE-$CI_COMMIT_REF_NAME"
Expand Down Expand Up @@ -95,7 +95,7 @@ stages: # ---------------------------------------------------------------------
script:
- cd IntegrationTests/${PROJ_NAME}/script
- pwd; ls -la; #debug
- vivado -mode batch -source common/script/synth.tcl
- vivado -mode batch -source common/script/synth.tcl | awk 'BEGIN{IGNORECASE=1} /^error/ {exit_code=1;} // {print $0;} END{exit exit_code}'
artifacts:
when: on_success
name: "$CI_JOB_NAME-$CI_JOB_STAGE-$CI_COMMIT_REF_NAME"
Expand Down Expand Up @@ -262,7 +262,6 @@ MC-vivado-hls-build:
PROJ_NAME: "MC"
MP-vivado-hls-build:
<<: *template_hls-build
allow_failure: true
needs: ["download", "MP-quality-check"]
variables:
EXECUTABLE: 'vivado_hls'
Expand Down Expand Up @@ -357,7 +356,6 @@ topPRMEMC-check-results:
- topPRMEMC-sim
topTETC-check-results:
<<: *template_check-results
allow_failure: true # FIXME: remove after all errors are fixed
variables:
VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
PROJ_NAME: "TETC"
Expand All @@ -366,7 +364,6 @@ topTETC-check-results:
- topTETC-sim
topIRVMR-check-results:
<<: *template_check-results
allow_failure: true # FIXME: remove after all errors are fixed
variables:
VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
PROJ_NAME: "IRVMR"
Expand Down
13 changes: 9 additions & 4 deletions IntegrationTests/common/hdl/FileReader.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -159,10 +159,16 @@ begin

if (NUM_BINS > 1) then
-- Get memory bin
read(LINE_IN, CHAR);
read(LINE_IN, CHAR); -- 0
read(LINE_IN, CHAR); -- x
read(LINE_IN, CHAR); -- 0
read(LINE_IN, CHAR); -- digit
char2int(CHAR, MEM_BIN);
read(LINE_IN, CHAR);
read(LINE_IN, CHAR);
read(LINE_IN, CHAR); -- space
read(LINE_IN, CHAR); -- 0
read(LINE_IN, CHAR); -- x
read(LINE_IN, CHAR); -- 0
read(LINE_IN, CHAR); -- digit
char2int(CHAR, POS_IN_MEM_BIN);
end if;

Expand All @@ -171,7 +177,6 @@ begin
if (CHAR = 'x') then -- ... until the next x
CNT_X_CHAR := CNT_X_CHAR + 1;
if ((NUM_BINS > 1 and CNT_X_CHAR = NUM_X_CHAR_BINNED) or
(NUM_BINS = 1 and CNT_X_CHAR = 1 and RAM_WIDTH = 36 and NUM_PAGES = 2) or -- Bodge for IL as they are unbinned but only contain one 'x'
(NUM_BINS = 1 and CNT_X_CHAR = NUM_X_CHAR_UNBINNED)) then -- No. of 'x' chars reached
-- Found data word.
FOUND_WORD := true;
Expand Down
14 changes: 11 additions & 3 deletions IntegrationTests/common/hdl/FileReaderFIFO.vhd
Original file line number Diff line number Diff line change
Expand Up @@ -53,12 +53,16 @@ procFile : process(CLK)
variable LINE_IN : line;
variable BX_CNT : integer := -1; --! Event counter
variable DATA_CNT : natural := MAX_ENTRIES; --! Current count of data from within current page.
constant NUM_X_CHAR : natural := 2; --! Count of 'x' characters in line, before value to read
variable CNT_X_CHAR : natural := 0; --! Current count of 'x' characters
variable CHAR : character; --! Character
variable FOUND_WORD : boolean := false;
variable emDATA : std_logic_vector(EMDATA_WIDTH-1 downto 0) := (others => '0');
variable LOOPING : boolean := true; --! Need another loop to make output.
variable CREATE_DUMMY_DATA : boolean := false; --! Inventing null data.
variable line_is_read : boolean := true; -- LINE_IN has been read by external module


begin

if rising_edge(CLK) then
Expand Down Expand Up @@ -147,13 +151,17 @@ begin

FOUND_WORD := false;
EMPTY_NEG <= '1'; -- There is stub to be read
CNT_X_CHAR := 0; -- Reset 'x' character counter

rd_col : while (LINE_IN'length > 0) loop -- Loop over the columns
read(LINE_IN, CHAR); -- Read chars ...
if (CHAR = 'x') then -- ... until the x
-- Found data word.
FOUND_WORD := true;
hread(line_in, emDATA(LINE_IN'length*4-1 downto 0)); -- Read remainer of line as hex.
CNT_X_CHAR := CNT_X_CHAR + 1;
if (CNT_X_CHAR = NUM_X_CHAR) then
-- Found data word.
FOUND_WORD := true;
hread(line_in, emDATA(LINE_IN'length*4-1 downto 0)); -- Read remainer of line as hex.
end if;
end if;
end loop rd_col;

Expand Down
1 change: 1 addition & 0 deletions IntegrationTests/common/script/CompareMemPrintsFW.py
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre

if is_binned:
bin, data = val
bin = bin.replace("0x","")
else:
data = val

Expand Down
75 changes: 46 additions & 29 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -80,46 +80,35 @@ These correspond to LUT used internally by the algo steps.
The files that are downloaded by emData/download.sh were created by the CMSSSW L1 track emulation, with the the following recipe (adapted from the [L1TrackSoftware TWiki](https://twiki.cern.ch/twiki/bin/view/CMS/L1TrackSoftware)).

```bash
cmsrel CMSSW_11_3_0_pre3
cd CMSSW_11_3_0_pre3/src/
cmsenv
git cms-checkout-topic -u cms-L1TK:fw_synch_210611
git clone https://github.com/cms-data/L1Trigger-TrackFindingTracklet.git L1Trigger/TrackFindingTracklet/data
cmsrel CMSSW_12_0_0_pre4
cd CMSSW_12_0_0_pre4/src/
cmsenv
git cms-checkout-topic -u cms-L1TK:fw_synch_220220
```

A few cfg changes were made in order to output test vectors & lookup tables, adjust truncation, and to disable multiple matches in the MatchCalculator. This required editing parameter values in L1Trigger/TrackFindingTracklet/interface/Settings.h to match the following excerpts:
A few configuration changes were made in order to output test vectors and lookup tables and adjust truncation. This required editing parameter values in L1Trigger/TrackFindingTracklet/interface/Settings.h to match the following excerpts:

```c++
//--- These used to create files needed by HLS code.
bool writeMem_{true}; //If true will print out content of memories (between algo steps) to files
bool writeTable_{true}; //If true will print out content of LUTs to files
bool writeConfig_{true}; //If true will print out the autogenerated configuration as files
//IR should be set to 108 to match the FW for the summer chain, but ultimately should be at 156
std::unordered_map<std::string, unsigned int> maxstep_{{"IR", 156}, //IR will run at a higher clock speed to handle
//input links running at 25 Gbits/s
//Set to 108 to match firmware project 240 MHz clock
bool writeHLSInvTable_{true}; //Write out tables of drinv and invt in tracklet calculator for HLS module
//--- These used to create files needed by HLS code.
bool writeMem_{false}; //If true will print out content of memories (between algo steps) to files
bool writeTable_{false}; //If true will print out content of LUTs to files
bool writeConfig_{false}; //If true will print out the autogenerated configuration as files
// When false, match calculator does not save multiple matches, even when doKF=true.
// This is a temporary fix for compatibilty with HLS. We will need to implement multiple match
// printing in emulator eventually, possibly after CMSSW-integration inspired rewrites
// Use false when generating HLS files, use true when doing full hybrid tracking
bool doMultipleMatches_{false};
bool writeHLSInvTable_{false}; //Write out tables of drinv and invt in tracklet calculator for HLS module
```

N.B. In future, better agreement with FW can be achieved by also setting the following parameter values in L1Trigger/TrackFindingTracklet/interface/Settings.h . This was *not done* for the existing emData/ files, but is recommended if generating new ones:

```c++
//Number of processing steps for one event (108=18TM*240MHz/40MHz)
// Change IR & TE from default values -- leave others unchanged.
std::unordered_map<std::string, unsigned int> maxstep_{{"IR", 108}, ... , {"TE", 107}}, ...}'
```
In addition, if you would like to run the configuration with the combined modules (i.e., the TrackletProcessor and MatchProcessor), you can do this by setting

In addition, if you'd like to run the Summer Chain configuration, you can do this by setting
```c++
bool reduced_{true}; // use reduced (Summer Chain) config
bool combined_{true}; // use combined TP (TE+TC) and MP (PR+ME+MC) configuration
```

Expand All @@ -129,15 +118,43 @@ Then compilation was done with the usual command:
scram b -j8
```

Finally, the maximum number of events in L1Trigger/TrackFindingTracklet/test/L1TrackNtupleMaker_cfg.py was set to 100:
The maximum number of events in L1Trigger/TrackFindingTracklet/test/L1TrackNtupleMaker_cfg.py was set to 100:

```python
process.maxEvents = cms.untracked.PSet(input = cms.untracked.int32(100))
```

and the emulation run:
Also, the following customization is needed:

```python
# HYBRID: prompt tracking
if (L1TRKALGO == 'HYBRID'):
process.TTTracksEmulation = cms.Path(process.L1HybridTracks)
process.TTTracksEmulationWithTruth = cms.Path(process.L1HybridTracksWithAssociators)

# Add the following two lines
from L1Trigger.TrackFindingTracklet.Customize_cff import *
fwConfig( process )
```

Finally, if you would like to run the reduced configuration used for the summer/skinny chain, change the algorithm to HYBRID_REDUCED:

```python
# Set L1 tracking algorithm:
# 'HYBRID' (baseline, 4par fit) or 'HYBRID_DISPLACED' (extended, 5par fit).
# 'HYBRID_NEWKF' (baseline, 4par fit, with bit-accurate KF emulation),
# 'HYBRID_REDUCED' to use the "Summer Chain" configuration with reduced inputs.
# (Or legacy algos 'TMTT' or 'TRACKLET').
L1TRKALGO = 'HYBRID_REDUCED'
```

The emulation is then run with:

```bash
cd L1Trigger/TrackFindingTracklet/test/
Expand Down
71 changes: 30 additions & 41 deletions TrackletAlgorithm/MatchCalculator.h
Original file line number Diff line number Diff line change
Expand Up @@ -360,16 +360,6 @@ void MatchCalculator(BXType bx,
read[i] = false;
}

// MC_L3PHIC mask {1: on, 0: off}
//static const uint16_t FML1L2 = 1 << shift_L1L2;
//static const uint16_t FML2L3 = 0 << shift_L2L3;
//static const uint16_t FML3L4 = 0 << shift_L3L4;
//static const uint16_t FML5L6 = 1 << shift_L5L6;
//static const uint16_t FMD1D2 = 0 << shift_D1D2;
//static const uint16_t FMD3D4 = 0 << shift_D3D4;
//static const uint16_t FML1D1 = 0 << shift_L1D1;
//static const uint16_t FML2D1 = 0 << shift_L2D1;

// Variables for the merger
// layer 1 variables
bool read_L1_1 = false;
Expand Down Expand Up @@ -446,6 +436,8 @@ void MatchCalculator(BXType bx,
FullMatch<FMTYPE> bestmatch;
bool goodmatch = false;

ap_uint<1> inc_fm = 1;


//-----------------------------------------------------------------------------------------------------------
//-------------------------------- DATA PROCESSING STARTS ---------------------------------------------------
Expand All @@ -461,7 +453,7 @@ void MatchCalculator(BXType bx,
ap_uint<kNBits_MemAddr> nmcout8 = 0;
MC_LOOP: for (ap_uint<kNBits_MemAddr> istep = 0; istep < kMaxProc - kMaxProcOffset(module::MC); istep++)
{

#pragma HLS PIPELINE II=1

// Pick up number of candidate matches for each CM memory
Expand Down Expand Up @@ -763,6 +755,11 @@ void MatchCalculator(BXType bx,
id_next = projid;
bool newtracklet = (istep==0 || (id_next != id))? true : false;

//increment full match memories
if (newtracklet) {
inc_fm = 1;
}

// Stub parameters
typename AllStub<ASTYPE>::ASR stub_r = stub.getR();
typename AllStub<ASTYPE>::ASZ stub_z = stub.getZ();
Expand All @@ -778,6 +775,7 @@ void MatchCalculator(BXType bx,
typename AllProjection<APTYPE>::AProjPHIDER proj_phid = proj.getPhiDer();
typename AllProjection<APTYPE>::AProjRZDER proj_zd = proj.getRZDer();


// Calculate residuals
// Get phi and z correction
ap_int<22> full_phi_corr = stub_r * proj_phid; // full corr has enough bits for full multiplication
Expand All @@ -798,7 +796,6 @@ void MatchCalculator(BXType bx,
ap_int<18> shiftstubphi = stub_phi_long << kPhi0_shift; // shift
ap_int<18> shiftprojphi = proj_phi_long << (kShift_phi0bit - 1 + kPhi0_shift); // shift
ap_int<17> delta_phi = shiftstubphi - shiftprojphi;
ap_uint<13> abs_delta_z = iabs<13>( delta_z_fact ); // absolute value of delta z
ap_uint<17> abs_delta_phi = iabs<17>( delta_phi ); // absolute value of delta phi

// Full match parameters
Expand All @@ -825,7 +822,7 @@ void MatchCalculator(BXType bx,
best_delta_phi = (newtracklet)? LUT_matchcut_phi[proj_seed] : best_delta_phi;

// Check that matches fall within the selection window of the projection
if ((abs_delta_z <= LUT_matchcut_z[proj_seed]) && (abs_delta_phi <= best_delta_phi)){
if ((delta_z_fact < LUT_matchcut_z[proj_seed]) && (delta_z_fact >= -LUT_matchcut_z[proj_seed]) && (abs_delta_phi <= best_delta_phi)){
// Update values of best phi parameters, so that the next match
// will be compared to this value instead of the original selection cut
best_delta_phi = abs_delta_phi;
Expand All @@ -835,68 +832,60 @@ void MatchCalculator(BXType bx,
goodmatch_next = true;
projseed_next = proj_seed;
}
else if (newtracklet){ // if is a new tracklet, do not make a match because it didn't pass the cuts
bestmatch_next = FullMatch<FMTYPE>();
goodmatch_next = false;
projseed_next = -1;
}
else { // if current match did not pass, but it is not a new tracklet, keep the previous best match for that tracklet
bestmatch_next = bestmatch;
goodmatch_next = goodmatch;
projseed_next = projseed;
}

if(newtracklet && goodmatch==true) { // Write out only the best match, based on the seeding
switch (projseed) {
if(goodmatch_next&&valid_L3) {
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switch (projseed_next) {
case 0:
if(FMMask<LAYER, PHISEC, TF::L1L2>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L1L2>()].write_mem(bx,bestmatch,nmcout1); // L1L2 seed
nmcout1++;
fullmatch[FMCount<LAYER, PHISEC, TF::L1L2>()].write_mem(bx,bestmatch_next,nmcout1+inc_fm-1); // L1L2 seed
nmcout1+=inc_fm;
}
break;
case 1:
if(FMMask<LAYER, PHISEC, TF::L2L3>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L2L3>()].write_mem(bx,bestmatch,nmcout2); // L2L3 seed
nmcout2++;
fullmatch[FMCount<LAYER, PHISEC, TF::L2L3>()].write_mem(bx,bestmatch_next,nmcout2+inc_fm-1); // L2L3 seed
nmcout2+=inc_fm;
}
break;
case 2:
if(FMMask<LAYER, PHISEC, TF::L3L4>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L3L4>()].write_mem(bx,bestmatch,nmcout3); // L3L4 seed
nmcout3++;
fullmatch[FMCount<LAYER, PHISEC, TF::L3L4>()].write_mem(bx,bestmatch_next,nmcout3+inc_fm-1); // L3L4 seed
nmcout3+=inc_fm;
}
break;
case 3:
if(FMMask<LAYER, PHISEC, TF::L5L6>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L5L6>()].write_mem(bx,bestmatch,nmcout4); // L5L6 seed
nmcout4++;
fullmatch[FMCount<LAYER, PHISEC, TF::L5L6>()].write_mem(bx,bestmatch_next,nmcout4+inc_fm-1); // L5L6 seed
nmcout4+=inc_fm;
}
break;
case 4:
if(FMMask<LAYER, PHISEC, TF::D1D2>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::D1D2>()].write_mem(bx,bestmatch,nmcout5); // D1D2 seed
nmcout5++;
fullmatch[FMCount<LAYER, PHISEC, TF::D1D2>()].write_mem(bx,bestmatch_next,nmcout5+inc_fm-1); // D1D2 seed
nmcout5+=inc_fm;
}
break;
case 5:
if(FMMask<LAYER, PHISEC, TF::D3D4>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::D3D4>()].write_mem(bx,bestmatch,nmcout6); // D3D4 seed
nmcout6++;
fullmatch[FMCount<LAYER, PHISEC, TF::D3D4>()].write_mem(bx,bestmatch_next,nmcout6+inc_fm-1); // D3D4 seed
nmcout6+=inc_fm;
}
break;
case 6:
if(FMMask<LAYER, PHISEC, TF::L1D1>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L1D1>()].write_mem(bx,bestmatch,nmcout7); // L1D1 seed
nmcout7++;
fullmatch[FMCount<LAYER, PHISEC, TF::L1D1>()].write_mem(bx,bestmatch_next,nmcout7+inc_fm-1); // L1D1 seed
nmcout7+=inc_fm;
}
break;
case 7:
if(FMMask<LAYER, PHISEC, TF::L2D1>()) {
fullmatch[FMCount<LAYER, PHISEC, TF::L2D1>()].write_mem(bx,bestmatch,nmcout8); // L2D1 seed
nmcout8++;
fullmatch[FMCount<LAYER, PHISEC, TF::L2D1>()].write_mem(bx,bestmatch_next,nmcout8+inc_fm-1); // L2D1 seed
nmcout8+=inc_fm;
}
break;
}
inc_fm=0;
}

// pipeline the bestmatch registers
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