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Link Rocket and T1 for RocketT1Tile #684

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wants to merge 140 commits into from
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Link Rocket and T1 for RocketT1Tile #684

wants to merge 140 commits into from

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sequencer
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  • [rtl] migrate T1 to FixedIOModule
  • [nix] use chisel#sequencer/t1 to workaround bug
  • [nix] bump upickle
  • [build system] add rocketv build target
  • [build system] implement the generic Elaborator trait
  • [build system] add rocketv to elaborator
  • [rocketv] copy ALU into rocketv project
  • [rocketv] migrate ALU
  • [rocketv] add elaborator for ALU
  • [rocketv] copy AMOALU into rocketv project
  • [rocketv] migrate AMOALU
  • [rocketv] add elaborator for AMOALU
  • [rocketv] copy Breakpoint into rocketv project
  • [rocketv] migrate BreakpointUnit
  • [rocketv] add elaborator for BreakpointUnit
  • [rocketv] copy BTB into rocketv project
  • [rocketv] migrate PopCountAtLeast
  • [rocketv] copy ReplacementPolicy into rocketv project
  • [rocketv] migrate Replacement
  • [rocketv] migrate BTB
  • [rocketv] add elaborator for BTB
  • [rocketv] copy CSR into rocketv project
  • [nix] bump rvdecoderdb for Causes fix
  • [rocketv] migrate CSR
  • [rocketv] add elaborator for CSR
  • [rocketv] migrate Decoder
  • [rocketv] add elaborator for Decoder
  • [rocketv] copy RVCExpander into rocketv project
  • [rocketv] migrate RVCExpander
  • [rocketv] add elaborator for RVCExpander
  • [rocketv] copy IBuf into rocketv project
  • [rocketv] migrate IBuf
  • [rocketv] add elaborator for IBuf
  • [rocketv] copy Multipler into rocketv project
  • [rocketv] migrate MulDiv and PipelinedMultiplier
  • [rocketv] add elaborator for MulDiv and PipelinedMultiplier
  • [rocketv] copy PMA into rocketv project
  • [rocketv] migrate PMAChecker
  • [rocketv] add elaborator for PMAChecker
  • [rocketv] copy PMP into rocketv project
  • [rocketv] migrate PMPChecker
  • [rocketv] add elaborator for PMAChecker
  • [rocketv] copy PTW into rocketv project
  • [rocketv] copy ECC into rocketv project
  • [rocketv] migrate PTW
  • [rocketv] add elaborator for PTW
  • [rocketv] copy ICache into rocketv project
  • [rocketv] migrate ICache
  • [rocketv] add elaborator for ICache
  • [rocketv] copy FPU into rocketv project
  • [rocketv] migrate FPU
  • [rocketv] add elaborator for FPU
  • [rocketv] copy TLB into rocketv project
  • [rocketv] migrate TLB
  • [rocketv] add elaborator for TLB
  • [rocketv] copy DCache into rocketv project
  • [rocketv] migrate DCache
  • [rocketv] add elaborator for DCache
  • [rocketv] copy Frontend into rocketv project
  • [rocketv] migrate Frontend
  • [rocketv] add elaborator for Frontend
  • [rocketv] copy RocketCore into rocketv project
  • [rocketv] migrate Rocket
  • [rocketv] add elaborator for Rocket
  • [rocketv] copy RocketTile into rocketv project
  • [rocketv] implementing RocketTile
  • [rocketv] add elaborator for RocketTile
  • [nix]: add rocketv derivation
  • [nix] add rocketv-mlirbc
  • [nix] add rocketv-rtl target
  • [nix] add new derivation rocketv-verilated-csrc
  • [rocketemu] implement TestBench for RocketV Emulator
  • [nix] add rocketv into elaborator source
  • [nix] use elaborator for Rocket generate
  • [dpi] expose AXI4 agent as C-API
  • [nix] add scope for rocketemu attribute
  • [rocketemu] implemented rocket driver
  • [rocketemu] update TestBench implementation
  • [rocketemu] update DPI C binding
  • [nix] add riscv-tests into overlay
  • [doc] add document about rocket emulator
  • [rocketemu] migrate AXI from master
  • [rocketemu] implement waveform generate
  • [rocketemu] add missing watchdog call
  • [rocketemu] Requires a longer reset.
  • [rocketemu] fix wrong size
  • [rocketemu] refactor AXI read functions and remove the read alignment
  • [rocketv] fix DCache axi read.
  • [build system] add t1-rocketv in build system for link t1 with rocket
  • [rockett1] draft Tile

@sequencer sequencer changed the base branch from master to real-rocket-v July 24, 2024 10:14
@sequencer sequencer force-pushed the rocket-t1 branch 2 times, most recently from 68614ab to 94cdc3f Compare July 24, 2024 19:10
@sequencer sequencer force-pushed the rocket-t1 branch 3 times, most recently from 90dffdf to b81fdf8 Compare July 26, 2024 06:17
Avimitin and others added 15 commits August 6, 2024 12:10
@Avimitin @sequencer
[nix] bump buddy-mlir
3c1e320 
Signed-off-by: Avimitin <dev@avimit.in>
@Lucas-Wye @sequencer
[rtl] support zvbb
fc61224
@Avimitin @sequencer
[nix] bump rvv-codegen
d8d0ff5 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[ci] add psyduck into CI
420460a 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[nix] fix codegen compile for zvbb insn
237fbb5 
Signed-off-by: Avimitin <dev@avimit.in>
@sequencer
[ci] dont patch elf for VCS result
766c5e3
@Avimitin @sequencer
[deps] Bump T1 dependencies
755f0f1
@Avimitin @sequencer
[nix] add standalone LLVM build for buddy-mlir
83f6099 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[nix] add Python module support for buddy-mlir
23948ba 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[pytorch] add demo workload
f2291a6 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[pytorch] use file write instead of print
f2970b4 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[tests] fix trace emu result
a527de3 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @sequencer
[tests] add build system for PyTorch test cases
e9b7c7b
@Avimitin @sequencer
[doc] add document for creating PyTorch tests
73e22ab
@Avimitin @sequencer
[ci] add PyTorch tests into CI
e196ba7 
Only add for blastoise cuz the pytorch.demo tests required zve32f.
PorterLu and others added 26 commits August 12, 2024 15:23
@PorterLu @Clo91eaf
[rocketemu] set the resetvector(width: 64) using information from an …
6b689fb 
…ELF file
@Clo91eaf
[rocketemu] add rustfmt
f199c04
@Clo91eaf
[rocketemu] build rocket offline difftest
53e21a2 
[rocketemu] catch watchdog timeout event in offline difftest

[rocketemu] optimize difftest loop

[rocketemu] should not soft link the nix result directly

[rocketemu] spike event record reg write idx with hex

[rocketemu] add support for msu priviledge

[rocketemu] skip check when spike/rtl reg write idx == 0
@Avimitin @Clo91eaf
[nix] refactor the rocketv subattr
d1caf73 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @Clo91eaf
[nix] rename default config to "meowth"
5c50fbb 
Signed-off-by: Avimitin <dev@avimit.in>
@SharzyL @Clo91eaf
[difftest] fix rust warnings
184f21e
@SharzyL @Clo91eaf
[script] fix nix attribute
a146489
@SharzyL @Clo91eaf
[cases] rvv_bench built from upstream source
6f6486e
@sequencer @Clo91eaf
[build system] add t1-rocketv in build system for link t1 with rocket
02931ac
@sequencer @Clo91eaf
[t1rocket] draft Tile
b88ff70 
- generate parameter json:  mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w
- generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile design --parameter ./T1RocketTile.json --run-firtool
@sequencer @Clo91eaf
[t1rocket] draft Testbench
871eb4e
@Avimitin @Clo91eaf
[t1rocket] fix elaborate
5af24d5 
nix develop ".#t1.elaborator.editable" -c mill -i elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --instructionSets rv_c
@Clo91eaf
[t1rocket] update TestBench
797d31d 
[t1rocket] update t1rocketemu TestBench.scala to build the config json
@Clo91eaf
[t1rocket] migrate difftest framework from t1 and update dpi from rocket
d3239e0 
[t1rocket] refactor load_from_payload function to improve readability and performance

[t1rocket] add elf crate dependency
@Avimitin @Clo91eaf
[elaborator] fix formatting
1e7eb5e
@Avimitin @Clo91eaf
[nix] add derivation for t1rocketemu
2fd9dd2
@Clo91eaf
[t1rocket] add missing dependencies and fix some bugs
dbc55c9 
[t1rocket] add timeout check

[t1rocket] use t1rocket_cosim_init instead of cosim_init to expose link bug
@Avimitin @Clo91eaf
[t1rocketemu] fix wrong mlirbc
29e7648 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin @Clo91eaf
[nix] fix wrong RTL reference
36d5c71 
Signed-off-by: Avimitin <dev@avimit.in>
@Clo91eaf
[t1rocket] add online difftest
9dd42cf 
[t1rocket] fix wrong get_resetvector

[t1rocket] fix unsafe extern "C" function signatures in dpi.rs

[t1rocket] update axi_read_load_store function to use correct size parameter

[t1rocket] add probes

[t1rocket] add last commit cycle during axi to control timeout

[t1rocket] add vrf score board check

[t1rocket] refactor event's name in offline difftest
@Clo91eaf
[t1rocket] add offline difftest
a96ba31
@qinjun-li @Clo91eaf
[rocketv] add rv_f in rocket.
a4448d8
@sequencer @Clo91eaf
fix for rebase
f4e1e31
@sequencer @Clo91eaf
fix for rebase
4ce33ae
@sequencer @Clo91eaf
fix for rebase
e1492ee
@Clo91eaf
[t1rocket] add quit to terminate simulation
2e45a61
@Avimitin
[nix] refactor features set filter to be more structural
c7d507a 
Signed-off-by: Avimitin <dev@avimit.in>
@Avimitin
[nix] refactor test case to allow t1rocket attr opt-in
a86154f 
Signed-off-by: Avimitin <dev@avimit.in>
@sequencer sequencer closed this Aug 12, 2024
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7 participants
@sequencer @Avimitin @Lucas-Wye @Clo91eaf @qinjun-li @PorterLu @SharzyL