[rtl] refactor mask unit.

t1/src/Bundles.scala

@@ -698,3 +698,63 @@ class T1Retire(xLen: Int) extends Bundle {
   val csr: ValidIO[T1CSRRetire] = Valid(new T1CSRRetire)
   val mem: ValidIO[EmptyBundle] = Valid(new EmptyBundle)
 }
+
+class MaskUnitGroupState(parameter: T1Parameter) extends Bundle {
+  val executeIndex: UInt = UInt(2.W)
+  val groupReadState: UInt = UInt(parameter.laneNumber.W)
+  val needRead: UInt = UInt(parameter.laneNumber.W)
+}
+
+class MaskUnitInstReq(parameter: T1Parameter) extends Bundle {
+  val instructionIndex: UInt         = UInt(parameter.instructionIndexBits.W)
+  val decodeResult:     DecodeBundle = Decoder.bundle(parameter.decoderParam)
+  val readFromScala: UInt = UInt(parameter.datapathWidth.W)
+  val eew: UInt = UInt(2.W)
+  val vm: Bool = Bool()
+  val vxrm: UInt = UInt(3.W)
+  val vd: UInt = UInt(5.W)
+}
+
+class MaskUnitExeReq(parameter: T1Parameter) extends Bundle {
+  // source1, read vs
+  val source1: UInt = UInt(parameter.datapathWidth.W)
+  // source2, read offset
+  val source2: UInt = UInt(parameter.datapathWidth.W)
+  val readOverlap = UInt(4.W)
+  val readLane: Vec[UInt] = Vec(4, UInt(log2Ceil(parameter.laneNumber).W))
+  val groupCounter: UInt = UInt(parameter.laneParam.groupNumberBits.W)
+}
+
+class MaskUnitReadReq(parameter: T1Parameter) extends Bundle {
+  val vs: UInt = UInt(5.W)
+  // source2, read offset
+  val offset: UInt = UInt(parameter.laneParam.vrfOffsetBits.W)
+  // Read which lane
+  val readLane: UInt = UInt(log2Ceil(parameter.laneNumber).W)
+}
+
+class MaskUnitReadQueue(parameter: T1Parameter) extends Bundle {
+  val vs: UInt = UInt(5.W)
+  // source2, read offset
+  val offset: UInt = UInt(parameter.laneParam.vrfOffsetBits.W)
+  // Which channel will this read request be written to?
+  val writeIndex: UInt = UInt(log2Ceil(parameter.laneNumber).W)
+}
+
+class MaskUnitWaitReadQueue(parameter: T1Parameter) extends Bundle {
+  // source1
+  val source1: Vec[UInt] = Vec(parameter.laneNumber, UInt(parameter.datapathWidth.W))
+  // source2
+  val source2: Vec[UInt] = Vec(parameter.laneNumber, UInt(parameter.datapathWidth.W))
+
+  val groupCounter: UInt = UInt(parameter.laneParam.groupNumberBits.W)
+  val executeIndex: UInt = UInt(2.W)
+
+  val needRead: UInt = UInt(parameter.laneNumber.W)
+}
+
+class MaskUnitWriteBundle(parameter: T1Parameter) extends Bundle {
+  val data: UInt = UInt(parameter.datapathWidth.W)
+  val mask: UInt = UInt((parameter.datapathWidth / 8).W)
+  val groupCounter: UInt = UInt(parameter.laneParam.groupNumberBits.W)
+}

t1/src/decoder/Decoder.scala

@@ -33,7 +33,7 @@ trait T1UopField extends T1DecodeFiled[UInt] with FieldName {
 }
 
 trait T1TopUopField extends T1DecodeFiled[UInt] with FieldName {
-  def chiselType: UInt = UInt(3.W)
+  def chiselType: UInt = UInt(5.W)
 }
 
 trait T1fpExecutionTypeUopField extends T1DecodeFiled[UInt] with FieldName {
@@ -227,14 +227,14 @@ object Decoder {
 
   object topUop extends T1TopUopField {
     override def genTable(pattern: T1DecodePattern): BitPat = pattern.topUop.value match {
-      case _: TopT0.type => BitPat("b000")
-      case _: TopT1.type => BitPat("b001")
-      case _: TopT2.type => BitPat("b010")
-      case _: TopT3.type => BitPat("b011")
-      case _: TopT5.type => BitPat("b101")
-      case _: TopT6.type => BitPat("b110")
-      case _: TopT7.type => BitPat("b111")
-      case _ => BitPat.dontCare(3)
+      case _: TopT0.type => BitPat("b00000")
+      case _: TopT1.type => BitPat("b00001")
+      case _: TopT2.type => BitPat("b00010")
+      case _: TopT3.type => BitPat("b00011")
+      case _: TopT5.type => BitPat("b00101")
+      case _: TopT6.type => BitPat("b00110")
+      case _: TopT7.type => BitPat("b00111")
+      case _ => BitPat.dontCare(5)
     }
   }
 

t1/src/sequencer/MaskCompress.scala

@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
+
+package org.chipsalliance.t1.rtl
+
+import chisel3._
+import chisel3.util._
+
+class CompressInput(parameter: T1Parameter) extends Bundle {
+  val vm: Bool = Bool()
+  val eew: UInt = UInt(2.W)
+  val uop: UInt = UInt(3.W)
+  val readFromScalar: UInt = UInt(parameter.datapathWidth.W)
+  val source1: UInt = UInt((parameter.laneNumber * parameter.datapathWidth).W)
+  val source2: UInt = UInt((parameter.laneNumber * parameter.datapathWidth).W)
+  val groupCounter: UInt = UInt(parameter.laneParam.groupNumberBits.W)
+  val lastCompress: Bool = Bool()
+}
+
+class CompressOutput(parameter: T1Parameter) extends Bundle {
+  val data: UInt = UInt((parameter.laneNumber * parameter.datapathWidth).W)
+  val mask: UInt = UInt((parameter.laneNumber * parameter.datapathWidth / 8).W)
+  val compressValid: Bool = Bool()
+}
+
+class MaskCompress(parameter: T1Parameter) extends Module {
+  val in: CompressInput = IO(Input(new CompressInput(parameter)))
+  val out: CompressOutput = IO(Input(new CompressOutput(parameter)))
+  val newInstruction: Bool = IO(Input(Bool()))
+
+  val maskSize: Int = parameter.laneNumber * parameter.datapathWidth / 8
+
+  // Source1 alignment
+  val source1Aligned: UInt = Wire(UInt(maskSize.W))
+  // TODO: Align and align in advance
+  source1Aligned := in.source1
+  val compress = in.uop === "b001".U
+  val viota = in.uop === "b000".U
+  val mv = in.uop === "b101".U
+
+  val eew1H: UInt = UIntToOH(in.eew)(2, 0)
+  val compressInit: UInt = RegInit(0.U(log2Ceil(parameter.vLen).W))
+  val compressVec: Vec[UInt] = Wire(Vec(maskSize, UInt(compressInit.getWidth.W)))
+  val compressMaskVec: Seq[Bool] = source1Aligned.asBools
+  val compressCount: UInt = compressMaskVec.zipWithIndex.foldLeft(compressInit) {
+    case (pre, (mask, index)) =>
+      compressVec(index) := pre
+      pre + mask
+  }
+  // todo: compress update
+  compressInit := Mux(newInstruction, 0.U, compressCount)
+
+  val viotaResult: UInt = Mux1H(eew1H,
+    Seq(1, 2, 4).map { eew =>
+      VecInit(Seq.tabulate(parameter.laneNumber) { index =>
+        // data width: eew * 8, data path 32, need [4 / eew] element
+        val dataSize = 4 / eew
+        val res: Seq[UInt] = Seq.tabulate(dataSize) { i =>
+          compressVec(dataSize * index + i)(eew * 8 - 1, 0)
+        }
+        // each data path
+        VecInit(res).asUInt
+      }).asUInt
+    }
+  )
+  val viotaMask: UInt = Mux1H(eew1H,
+    Seq(1, 2, 4).map { eew =>
+      VecInit(Seq.tabulate(parameter.laneNumber) { index =>
+        val dataSize = 4 / eew
+        val res: Seq[UInt] = Seq.tabulate(dataSize) { i =>
+          Fill(eew, compressMaskVec(dataSize * index + i))
+        }
+        // 4 bit mask
+        VecInit(res).asUInt
+      }).asUInt
+    }
+  )
+
+  val tailCount = compressInit
+  val compressDataReg = RegInit(0.U((parameter.laneNumber * parameter.datapathWidth).W))
+  val compressDataVec = Seq(1, 2, 4).map { eew =>
+    VecInit(Seq.tabulate(parameter.laneNumber * 2) { index =>
+      val useTail = index.U < tailCount
+      val tailData = cutUInt(compressDataReg, eew)(index)
+      val maskSize = 4 * parameter.laneNumber / eew
+      val hitReq = Seq.tabulate(maskSize)( maskIndex => compressVec(maskIndex) === index.U )
+      val selectReqData = Mux1H(
+        hitReq,
+        cutUInt(in.source2, eew)
+      )
+      Mux(useTail, tailData, selectReqData)
+    }).asUInt
+  }
+  val compressResult: UInt = Mux1H(eew1H, compressDataVec)
+
+  // todo: connect & update compressInit
+  val compressTailMask = Wire(UInt(out.mask.getWidth.W))
+  val compressTailValid = Wire(Bool())
+
+  val mvMask = Mux1H(eew1H, Seq(1.U, 3.U, 15.U))
+  val mvData = Mux1H(
+    eew1H,
+    Seq(
+      in.readFromScalar(7, 0),
+      in.readFromScalar(15, 0),
+      in.readFromScalar
+    )
+  )
+
+  out.mask := Mux1H(Seq(
+    compress -> compressResult,
+    viota -> viotaResult,
+    mv -> mvData,
+  ))
+
+  // todo: compressMask
+  out.mask := Mux1H(Seq(
+    compress -> compressTailMask,
+    viota -> viotaMask,
+    mv -> mvMask,
+  ))
+
+  // todo
+  out.compressValid := false.B
+}

t1/src/sequencer/MaskExtend.scala

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
+
+package org.chipsalliance.t1.rtl
+
+import chisel3._
+import chisel3.util._
+
+class ExtendInput(parameter: T1Parameter) extends Bundle {
+  val eew: UInt = UInt(2.W)
+  val uop: UInt = UInt(3.W)
+  val source2: UInt = UInt((parameter.laneNumber * parameter.datapathWidth).W)
+  val groupCounter: UInt = UInt(parameter.laneParam.groupNumberBits.W)
+}
+
+class MaskExtend(parameter: T1Parameter) extends Module {
+  val in: ExtendInput = IO(Input(new ExtendInput(parameter)))
+  val out: UInt = IO(Output(UInt(parameter.datapathWidth.W)))
+
+  val eew1H: UInt = UIntToOH(in.eew)(2, 0)
+
+  val isMaskDestination: Bool = in.uop.andR
+  val maskDestinationResult:      UInt          = Mux1H(
+    eew1H,
+    Seq(4, 2, 1).map { groupSize =>
+      VecInit(cutUInt(in.source2, groupSize).
+        grouped(parameter.laneNumber).toSeq.
+        transpose.map(a => VecInit(a).asUInt)).asUInt
+    }
+  )
+
+  // extend
+  val sign: Bool = in.uop(0)
+  // extend ratio
+  // todo: Currently only vf2 and vf4
+  val extendRatio: Bool = in.uop(1)
+
+  // select source2
+  // extendRatio: 0 -> vf2; 1-> vf4
+  val source2: UInt = Mux(
+    extendRatio,
+    Mux1H(
+      UIntToOH(in.groupCounter(1, 0)),
+      cutUInt(in.source2, parameter.laneNumber * parameter.datapathWidth / 4)
+    ),
+    Mux1H(
+      UIntToOH(in.groupCounter(0)),
+      cutUInt(in.source2, parameter.laneNumber * parameter.datapathWidth / 2)
+    )
+  )
+
+  val extendResult: UInt = Mux1H(eew1H(2, 1), Seq(2, 4).map{ dataWidth =>
+    Mux1H(UIntToOH(extendRatio), Seq(2, 4).map { ratio =>
+      val resWidth = dataWidth * 8
+      val sourceWidth = resWidth / ratio
+      VecInit(cutUInt(source2, sourceWidth).map { sourceData =>
+        Fill(resWidth - sourceWidth, sourceData(sourceWidth - 1) && sign) ## sourceData
+      }).asUInt
+    })
+  })
+
+  out := Mux(isMaskDestination, maskDestinationResult, extendResult)
+}