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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc | ||
| index eaf6553ce..ee7121548 100644 | ||
| --- a/frontends/ast/genrtlil.cc | ||
| +++ b/frontends/ast/genrtlil.cc | ||
| @@ -841,6 +841,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun | ||
| } | ||
| if (!id_ast) | ||
| log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str()); | ||
| + if (id_ast->type == AST_TYPEDEF) { | ||
| + id_ast = id_ast->children[0]; | ||
| + } | ||
| if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) { | ||
| if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { | ||
| this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; |
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34 changes: 34 additions & 0 deletions
34
...black-parrot/black-parrot-patches/basejump_stl/0001-Replace-enum-logic-with-typedef.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,34 @@ | ||
| From 0677d0f5156b5afe8f54286ea690144da0547baa Mon Sep 17 00:00:00 2001 | ||
| From: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| Date: Wed, 26 Apr 2023 09:21:38 +0200 | ||
| Subject: [PATCH 1/3] Replace enum logic with typedef | ||
|
|
||
| Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| --- | ||
| bsg_cache/bsg_cache_dma_to_wormhole.v | 5 +++-- | ||
| 1 file changed, 3 insertions(+), 2 deletions(-) | ||
|
|
||
| diff --git a/bsg_cache/bsg_cache_dma_to_wormhole.v b/bsg_cache/bsg_cache_dma_to_wormhole.v | ||
| index 19e4fcf0..7959eb85 100644 | ||
| --- a/bsg_cache/bsg_cache_dma_to_wormhole.v | ||
| +++ b/bsg_cache/bsg_cache_dma_to_wormhole.v | ||
| @@ -137,13 +137,14 @@ module bsg_cache_dma_to_wormhole | ||
| ); | ||
|
|
||
| // send FSM | ||
| - enum logic [2:0] { | ||
| + typedef enum logic [2:0] { | ||
| SEND_RESET | ||
| , SEND_READY | ||
| , SEND_ADDR | ||
| , SEND_MASK | ||
| , SEND_DATA | ||
| - } send_state_n, send_state_r; | ||
| + } state_t; | ||
| + state_t send_state_n, send_state_r; | ||
|
|
||
|
|
||
| // Check if mask bits are all 1. | ||
| -- | ||
| 2.39.0 | ||
|
|
12 changes: 6 additions & 6 deletions
12
...black-parrot/0001-Replace-stream-op.patch → ...basejump_stl/0002-Replace-stream-op.patch
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93 changes: 93 additions & 0 deletions
93
...ts/black-parrot/black-parrot-patches/basejump_stl/0003-WIP-start-wires-from-index-0.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,93 @@ | ||
| From 638f88f8ea7f28d8f10d502033214ca6cc8cc696 Mon Sep 17 00:00:00 2001 | ||
| From: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| Date: Wed, 26 Apr 2023 15:06:28 +0200 | ||
| Subject: [PATCH 3/3] WIP: start wires from index 0 | ||
|
|
||
| Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| --- | ||
| bsg_noc/bsg_mesh_stitch.v | 51 ++++++++++++++++++++++----------------- | ||
| 1 file changed, 29 insertions(+), 22 deletions(-) | ||
|
|
||
| diff --git a/bsg_noc/bsg_mesh_stitch.v b/bsg_noc/bsg_mesh_stitch.v | ||
| index 6ccb8383..201dce61 100644 | ||
| --- a/bsg_noc/bsg_mesh_stitch.v | ||
| +++ b/bsg_noc/bsg_mesh_stitch.v | ||
| @@ -14,15 +14,22 @@ module bsg_mesh_stitch | ||
| , x_max_p = "inv" | ||
| , y_max_p = "inv" | ||
| , nets_p = 1 // optional parameter that allows for multiple networks to be routed together | ||
| + //typedef enum logic[2:0] {P=3'd0, W, E, N, S} Dirs; | ||
| + // recalculate assuming W = 0 and S = 0 | ||
| + , parameter logic [2:0] W2 = 0 /*W-W*/ | ||
| + , parameter logic [2:0] E2 = E-W | ||
| + , parameter logic [2:0] S2 = 0 /*S-S*/ | ||
| + , parameter logic [2:0] N2 = S-N /*S is larger*/ | ||
| + , parameter logic [2:0] SW2 = S-W /*S is larger*/ | ||
| ) | ||
| - (input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] outs_i // for each node, each direction | ||
| - , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] ins_o | ||
| + (input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] outs_i // for each node, each direction | ||
| + , output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][SW:0][width_p-1:0] ins_o | ||
|
|
||
| // these are the edge of the greater tile | ||
| - , input [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i | ||
| - , output [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o | ||
| - , input [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i | ||
| - , output [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o | ||
| + , input [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i | ||
| + , output [E2:W2][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o | ||
| + , input [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i | ||
| + , output [N2:S2][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o | ||
| ); | ||
|
|
||
| genvar r,c,net; | ||
| @@ -32,30 +39,30 @@ module bsg_mesh_stitch | ||
|
|
||
| for (r = 0; r < y_max_p; r=r+1) | ||
| begin: _r | ||
| - assign hor_o[E][r][net] = outs_i[r][x_max_p-1][net][E]; | ||
| - assign hor_o[W][r][net] = outs_i[r][0 ][net][W]; | ||
| + assign hor_o[E2-1][r][net] = outs_i[r][x_max_p-1][net][E2-1]; | ||
| + assign hor_o[W2][r][net] = outs_i[r][0 ][net][W2]; | ||
|
|
||
| for (c = 0; c < x_max_p; c=c+1) | ||
| begin: _c | ||
| - assign ins_o[r][c][net][S] = (r == y_max_p-1) | ||
| - ? ver_i[S][c][net] | ||
| - : outs_i[(r == y_max_p-1) ? r : r+1][c][net][N]; // ?: for warning | ||
| - assign ins_o[r][c][net][N] = (r == 0) | ||
| - ? ver_i[N][c][net] | ||
| - : outs_i[r ? r-1: 0][c][net][S]; // ?: to eliminate warning | ||
| - assign ins_o[r][c][net][E] = (c == x_max_p-1) | ||
| - ? hor_i[E][r][net] | ||
| - : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W]; // ?: for warning | ||
| - assign ins_o[r][c][net][W] = (c == 0) | ||
| - ? hor_i[W][r][net] | ||
| - : outs_i[r][c ? (c-1) :0][net][E]; // ?: to eliminate warning | ||
| + assign ins_o[r][c][net][N2] = (r == y_max_p-1) | ||
| + ? ver_i[N2][c][net] | ||
| + : outs_i[(r == y_max_p-1) ? r : r+1][c][net][S2]; // ?: for warning | ||
| + assign ins_o[r][c][net][S2] = (r == 0) | ||
| + ? ver_i[S2][c][net] | ||
| + : outs_i[r ? r-1: 0][c][net][N2]; // ?: to eliminate warning | ||
| + assign ins_o[r][c][net][E2-1] = (c == x_max_p-1) | ||
| + ? hor_i[E2-1][r][net] | ||
| + : outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W2]; // ?: for warning | ||
| + assign ins_o[r][c][net][W2] = (c == 0) | ||
| + ? hor_i[W2][r][net] | ||
| + : outs_i[r][c ? (c-1) :0][net][E2-1]; // ?: to eliminate warning | ||
| end // block: c | ||
| end // block: r | ||
|
|
||
| for (c = 0; c < x_max_p; c=c+1) | ||
| begin: _c | ||
| - assign ver_o[S][c][net] = outs_i[y_max_p-1][c][net][S]; | ||
| - assign ver_o[N][c][net] = outs_i[0 ][c][net][N]; | ||
| + assign ver_o[N2][c][net] = outs_i[y_max_p-1][c][net][N2]; | ||
| + assign ver_o[S2][c][net] = outs_i[0 ][c][net][S2]; | ||
| end | ||
| end // block: _n | ||
|
|
||
| -- | ||
| 2.39.0 | ||
|
|
6 changes: 3 additions & 3 deletions
6
...e-typedef-instead-of-anonymous-enum.patch → ...001-Replace-enum-logic-with-typedef.patch
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33 changes: 33 additions & 0 deletions
33
...rrot/black-parrot-patches/black-parrot/0002-Add-workaround-for-unsupported-typespec.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,33 @@ | ||
| From 0a5300004fc90bae4b0dbc214ff331e5a25cd5a6 Mon Sep 17 00:00:00 2001 | ||
| From: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| Date: Wed, 26 Apr 2023 09:17:48 +0200 | ||
| Subject: [PATCH 2/4] Add workaround for unsupported typespec | ||
|
|
||
| Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| --- | ||
| bp_common/src/include/bp_common_bedrock_if.svh | 6 +++++- | ||
| 1 file changed, 5 insertions(+), 1 deletion(-) | ||
|
|
||
| diff --git a/bp_common/src/include/bp_common_bedrock_if.svh b/bp_common/src/include/bp_common_bedrock_if.svh | ||
| index ac7acf8f..5118d0ee 100644 | ||
| --- a/bp_common/src/include/bp_common_bedrock_if.svh | ||
| +++ b/bp_common/src/include/bp_common_bedrock_if.svh | ||
| @@ -196,10 +196,14 @@ | ||
| `declare_bp_bedrock_header_width(addr_width_mp, mem_fwd_payload_width_lp, mem_fwd) \ | ||
| `declare_bp_bedrock_header_width(addr_width_mp, mem_rev_payload_width_lp, mem_rev) | ||
|
|
||
| + //declare_bp_bedrock_mem_payload_s macro defines `bp_bedrock_mem_fwd_payload_s` struct, | ||
| + //and creates typedef `bp_bedrock_mem_rev_payload_s` that is equal to | ||
| + //`bp_bedrock_mem_fwd_payload_s` but Surelog doesn't see it. Use | ||
| + //`bp_bedrock_mem_fwd_payload_s` directly for now. | ||
| `define declare_bp_bedrock_mem_if(addr_width_mp, did_width_mp, lce_id_width_mp, lce_assoc_mp) \ | ||
| `declare_bp_bedrock_mem_payload_s(did_width_mp, lce_id_width_mp, lce_assoc_mp); \ | ||
| `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_fwd); \ | ||
| - `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_rev_payload_s, mem_rev) \ | ||
| + `declare_bp_bedrock_header_s(addr_width_mp, bp_bedrock_mem_fwd_payload_s, mem_rev) \ | ||
|
|
||
| `define declare_bp_bedrock_if_widths(addr_width_mp, payload_width_mp, name_mp) \ | ||
| , localparam ``name_mp``_msg_payload_width_lp = payload_width_mp \ | ||
| -- | ||
| 2.39.0 | ||
|
|
86 changes: 86 additions & 0 deletions
86
.../black-parrot-patches/black-parrot/0003-WIP-Replace-stream-operator-without-reverse.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,86 @@ | ||
| From 7c93699a9c0002d110aec5c62843084ece7403ba Mon Sep 17 00:00:00 2001 | ||
| From: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| Date: Wed, 26 Apr 2023 15:04:59 +0200 | ||
| Subject: [PATCH 3/4] WIP: Replace stream operator without reverse | ||
|
|
||
| Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||
| --- | ||
| bp_me/src/v/cce/bp_cce_dir_segment.sv | 2 +- | ||
| bp_me/src/v/cce/bp_cce_pending_bits.sv | 4 ++-- | ||
| bp_me/src/v/cce/bp_cce_spec_bits.sv | 4 ++-- | ||
| bp_me/src/v/network/bp_me_addr_to_cce_id.sv | 2 +- | ||
| bp_top/test/common/bp_nonsynth_host.sv | 2 +- | ||
| 5 files changed, 7 insertions(+), 7 deletions(-) | ||
|
|
||
| diff --git a/bp_me/src/v/cce/bp_cce_dir_segment.sv b/bp_me/src/v/cce/bp_cce_dir_segment.sv | ||
| index 94abc422..20394392 100644 | ||
| --- a/bp_me/src/v/cce/bp_cce_dir_segment.sv | ||
| +++ b/bp_me/src/v/cce/bp_cce_dir_segment.sv | ||
| @@ -126,7 +126,7 @@ module bp_cce_dir_segment | ||
| logic [lg_num_cce_lp-1:0] cce_id_lo; | ||
| logic [hash_index_width_lp-1:0] set_id_lo; | ||
| // NOTE: reverse the address to use the low order bits for striping cache blocks across CCEs | ||
| - wire [lg_sets_lp-1:0] hash_addr_rev = { <<{addr_i[lg_block_size_in_bytes_lp+:lg_sets_lp]}}; | ||
| + wire [lg_sets_lp-1:0] hash_addr_rev = addr_i[lg_block_size_in_bytes_lp+:lg_sets_lp]; // TODO: reverse order | ||
|
|
||
| bsg_hash_bank | ||
| #(.banks_p(num_cce_p) // number of CCE's to spread way groups over | ||
| diff --git a/bp_me/src/v/cce/bp_cce_pending_bits.sv b/bp_me/src/v/cce/bp_cce_pending_bits.sv | ||
| index 517c79df..94edd948 100644 | ||
| --- a/bp_me/src/v/cce/bp_cce_pending_bits.sv | ||
| +++ b/bp_me/src/v/cce/bp_cce_pending_bits.sv | ||
| @@ -62,8 +62,8 @@ module bp_cce_pending_bits | ||
| // Address to way group hashing | ||
| // The address to use as input starts at addr_offset_p and is lg_cce_way_groups_lp bits in length | ||
| logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; | ||
| - wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; | ||
| - wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; | ||
| + wire [lg_cce_way_groups_lp-1:0] r_addr_rev = r_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order | ||
| + wire [lg_cce_way_groups_lp-1:0] w_addr_rev = w_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order | ||
| logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; | ||
|
|
||
| bsg_hash_bank | ||
| diff --git a/bp_me/src/v/cce/bp_cce_spec_bits.sv b/bp_me/src/v/cce/bp_cce_spec_bits.sv | ||
| index c0b87884..f6523067 100644 | ||
| --- a/bp_me/src/v/cce/bp_cce_spec_bits.sv | ||
| +++ b/bp_me/src/v/cce/bp_cce_spec_bits.sv | ||
| @@ -58,8 +58,8 @@ module bp_cce_spec_bits | ||
|
|
||
| // Address to way group hashing | ||
| logic [hash_idx_width_lp-1:0] r_wg_lo, w_wg_lo; | ||
| - wire [lg_cce_way_groups_lp-1:0] r_addr_rev = {<< {r_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; | ||
| - wire [lg_cce_way_groups_lp-1:0] w_addr_rev = {<< {w_addr_i[addr_offset_p+:lg_cce_way_groups_lp]}}; | ||
| + wire [lg_cce_way_groups_lp-1:0] r_addr_rev = r_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order | ||
| + wire [lg_cce_way_groups_lp-1:0] w_addr_rev = w_addr_i[addr_offset_p+:lg_cce_way_groups_lp];// TODO: reverse order | ||
| logic [lg_num_way_groups_lp-1:0] r_wg, w_wg; | ||
|
|
||
| bsg_hash_bank | ||
| diff --git a/bp_me/src/v/network/bp_me_addr_to_cce_id.sv b/bp_me/src/v/network/bp_me_addr_to_cce_id.sv | ||
| index d3100ed4..b8cd9e76 100644 | ||
| --- a/bp_me/src/v/network/bp_me_addr_to_cce_id.sv | ||
| +++ b/bp_me/src/v/network/bp_me_addr_to_cce_id.sv | ||
| @@ -48,7 +48,7 @@ module bp_me_addr_to_cce_id | ||
| // at the cache block granularity | ||
| logic [lce_sets_width_p-1:0] hash_addr_li; | ||
| logic [lg_num_cce_lp-1:0] cce_dst_id_lo; | ||
| - assign hash_addr_li = {<< {paddr_i[block_offset_lp+:lce_sets_width_p]}}; | ||
| + assign hash_addr_li = paddr_i[block_offset_lp+:lce_sets_width_p]; //TODO: reverse order | ||
| bsg_hash_bank | ||
| #(.banks_p(num_cce_p) // number of CCE's to spread way groups over | ||
| ,.width_p(lce_sets_width_p) // width of address input | ||
| diff --git a/bp_top/test/common/bp_nonsynth_host.sv b/bp_top/test/common/bp_nonsynth_host.sv | ||
| index 16dd997f..e62db586 100644 | ||
| --- a/bp_top/test/common/bp_nonsynth_host.sv | ||
| +++ b/bp_top/test/common/bp_nonsynth_host.sv | ||
| @@ -204,7 +204,7 @@ module bp_nonsynth_host | ||
| ); | ||
|
|
||
| // Convert to little endian | ||
| - wire [dword_width_gp-1:0] bootrom_data_reverse = {<<8{bootrom_data_lo}}; | ||
| + wire [dword_width_gp-1:0] bootrom_data_reverse = bootrom_data_lo; // TODO: reverse order | ||
|
|
||
| logic [dword_width_gp-1:0] bootrom_final_lo; | ||
| bsg_bus_pack | ||
| -- | ||
| 2.39.0 | ||
|
|
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