Updates for Yosys 0.43 #5778
kamilrakoczymain.yml
on: pull_request
Matrix: build-binaries
Build sv2v
2m 14s
Emit Workflow Info
0s
Style check
1m 55s
Test "Installation from source" from README
24m 53s
Upload GHA event file
2s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
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Ibex (Vivado synthesis)
6m 52s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 11s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
1h 7m
Large Designs Tests
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Opentitan (synthesis)
1h 12m
Large Designs Tests
/
VeeR-EH1 (synthesis)
6m 5s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
18m 44s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
41m 47s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
9m 12s
Test With Packaged Yosys
2m 35s
Test With Bundled Yosys
3m 17s
Matrix: Formal Verification Tests / tests-formal-verification
Release Package Installation Test
0s
Annotations
6 errors and 6 warnings
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Formal Verification Tests / simple
Process completed with exit code 1.
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Formal Verification Tests / yosys
Process completed with exit code 1.
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Formal Verification Tests / sv2v
Process completed with exit code 1.
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Parsing Tests / Surelog
Process completed with exit code 1.
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Parsing Tests / SystemVerilog Plugin
Process completed with exit code 1.
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Large Designs Tests / Opentitan 9d82960888 (synthesis)
Process completed with exit code 2.
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Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Upload GHA event file
The following actions uses Node.js version which is deprecated and will be forced to run on node20: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Deprecation notice: v1, v2, and v3 of the artifact actions
The following artifacts were uploaded using a version of actions/upload-artifact that is scheduled for deprecation: "binaries", "binaries-asan", "binaries-debian", "bp_e_bp_unicore_cfg.edif", "bsg-logs", "bsg-outputs", "event.json", "formal-verification-logs", "formal-verification-tests-list", "lowrisc_ibex_top_artya7_surelog_0.1.bit", "lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif", "opentitan-logs-full", "opentitan-logs-quick", "parsing_read-systemverilog_logs", "parsing_read-systemverilog_yosys-sv", "parsing_read-uhdm_logs", "parsing_read-uhdm_yosys-sv", "parsing_test-results", "plots", "sv2v", "top_artya7.bit".
Please update your workflow to use v4 of the artifact actions.
Learn more: https://github.blog/changelog/2024-04-16-deprecation-notice-v3-of-the-artifact-actions/
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries
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130 MB |
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binaries-asan
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1.02 GB |
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binaries-debian
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130 MB |
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bp_e_bp_unicore_cfg.edif
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60.6 MB |
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bsg-logs
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86.3 MB |
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bsg-outputs
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13.5 MB |
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event.json
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27.2 KB |
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formal-verification-logs
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607 MB |
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formal-verification-tests-list
|
53.7 KB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
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2.09 MB |
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lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif
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221 MB |
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opentitan-logs-full
|
164 MB |
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opentitan-logs-quick
|
39.2 MB |
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parsing_read-systemverilog_logs
|
15 MB |
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parsing_read-systemverilog_yosys-sv
|
323 KB |
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parsing_read-uhdm_logs
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16.3 MB |
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parsing_read-uhdm_yosys-sv
|
328 KB |
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parsing_test-results
Expired
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21.3 KB |
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plots
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23.1 MB |
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sv2v
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8.42 MB |
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top_artya7.bit
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2.09 MB |
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