Set parameterized desiredName on many system components #3641
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jerryz123
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sequencer
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Jun 10, 2024
jerryz123
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jerryz123
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This improves the naming stability of generated verilog by adding descriptive suffixes to module names. This makes it easier to determine where many important modules are instantiated.
Related issue:
Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
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