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refactor ALU.scala to chisel3 style #3039

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Sep 12, 2022
Merged

refactor ALU.scala to chisel3 style #3039

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59 changes: 30 additions & 29 deletions src/main/scala/rocket/ALU.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,28 +3,29 @@

package freechips.rocketchip.rocket

import Chisel._
import chisel3._
import chisel3.util.{BitPat, Fill, Cat, Reverse}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.tile.CoreModule

object ALU
{
val SZ_ALU_FN = 4
def FN_X = BitPat("b????")
def FN_ADD = UInt(0)
def FN_SL = UInt(1)
def FN_SEQ = UInt(2)
def FN_SNE = UInt(3)
def FN_XOR = UInt(4)
def FN_SR = UInt(5)
def FN_OR = UInt(6)
def FN_AND = UInt(7)
def FN_SUB = UInt(10)
def FN_SRA = UInt(11)
def FN_SLT = UInt(12)
def FN_SGE = UInt(13)
def FN_SLTU = UInt(14)
def FN_SGEU = UInt(15)
def FN_ADD = 0.U
def FN_SL = 1.U
def FN_SEQ = 2.U
def FN_SNE = 3.U
def FN_XOR = 4.U
def FN_SR = 5.U
def FN_OR = 6.U
def FN_AND = 7.U
def FN_SUB = 10.U
def FN_SRA = 11.U
def FN_SLT = 12.U
def FN_SGE = 13.U
def FN_SLTU = 14.U
def FN_SGEU = 15.U

def FN_DIV = FN_XOR
def FN_DIVU = FN_SR
Expand All @@ -47,15 +48,15 @@ object ALU
import ALU._

class ALU(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val dw = Bits(INPUT, SZ_DW)
val fn = Bits(INPUT, SZ_ALU_FN)
val in2 = UInt(INPUT, xLen)
val in1 = UInt(INPUT, xLen)
val out = UInt(OUTPUT, xLen)
val adder_out = UInt(OUTPUT, xLen)
val cmp_out = Bool(OUTPUT)
}
val io = IO(new Bundle {
val dw = Input(UInt(SZ_DW.W))
val fn = Input(UInt(SZ_ALU_FN.W))
val in2 = Input(UInt(xLen.W))
val in1 = Input(UInt(xLen.W))
val out = Output(UInt(xLen.W))
val adder_out = Output(UInt(xLen.W))
val cmp_out = Output(Bool())
})

// ADD, SUB
val in2_inv = Mux(isSub(io.fn), ~io.in2, io.in2)
Expand All @@ -66,7 +67,7 @@ class ALU(implicit p: Parameters) extends CoreModule()(p) {
val slt =
Mux(io.in1(xLen-1) === io.in2(xLen-1), io.adder_out(xLen-1),
Mux(cmpUnsigned(io.fn), io.in2(xLen-1), io.in1(xLen-1)))
io.cmp_out := cmpInverted(io.fn) ^ Mux(cmpEq(io.fn), in1_xor_in2 === UInt(0), slt)
io.cmp_out := cmpInverted(io.fn) ^ Mux(cmpEq(io.fn), in1_xor_in2 === 0.U, slt)

// SLL, SRL, SRA
val (shamt, shin_r) =
Expand All @@ -81,12 +82,12 @@ class ALU(implicit p: Parameters) extends CoreModule()(p) {
val shin = Mux(io.fn === FN_SR || io.fn === FN_SRA, shin_r, Reverse(shin_r))
val shout_r = (Cat(isSub(io.fn) & shin(xLen-1), shin).asSInt >> shamt)(xLen-1,0)
val shout_l = Reverse(shout_r)
val shout = Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r, UInt(0)) |
Mux(io.fn === FN_SL, shout_l, UInt(0))
val shout = Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r, 0.U) |
Mux(io.fn === FN_SL, shout_l, 0.U)

// AND, OR, XOR
val logic = Mux(io.fn === FN_XOR || io.fn === FN_OR, in1_xor_in2, UInt(0)) |
Mux(io.fn === FN_OR || io.fn === FN_AND, io.in1 & io.in2, UInt(0))
val logic = Mux(io.fn === FN_XOR || io.fn === FN_OR, in1_xor_in2, 0.U) |
Mux(io.fn === FN_OR || io.fn === FN_AND, io.in1 & io.in2, 0.U)
val shift_logic = (isCmp(io.fn) && slt) | logic | shout
val out = Mux(io.fn === FN_ADD || io.fn === FN_SUB, io.adder_out, shift_logic)

Expand Down