RoccBlackBox fix #3035
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RoccBlackBox fix #3035
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…s_rd; 2) incorrect behavior in synthesis result (tested on FPGA)
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jerryz123
approved these changes
Sep 6, 2022
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Fix 1: incorrect signal assigned to
rocc_resp_bits_rdinRoCCBlackBox;Fix 2: incorrect
RoccBlackBoxbehavior after logic synthesis (tested for Xilinx FPGA with Vivado).Related issue:
Type of change: bug report
Impact: no functional change
Development Phase: implementation
Release Notes
src/main/resources/vsrc/RoccBlackBox.vis modified to fix incorrect signal assignment and behavior in synthesis result