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Support incoherent access to ExtMem through SBus #2978

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merged 3 commits into from
Sep 14, 2022
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@jerryz123 jerryz123 commented May 6, 2022

I'm not sure if this approach is the best, but the provided functionality is useful.

This PR provides a new incohBase field to the MemoryPortParams. When set, this field creates an alias for the backing AXI4 mem and attaches that alias to the systembus. This provides a mechanism through which masters can directly access cacheable memory while bypassing a coherence manager.

For example, the default ExtMem region 0x8000_0000 : 0x9000_0000 can now also also be accessed at 0x10_8000_0000 - 0x10_9000_0000.

Type of change: new feature

Impact: API addition (no impact on existing code)

Development Phase: implementation

Release Notes

@jerryz123 jerryz123 requested review from terpstra and hcook May 6, 2022 21:54
@jerryz123 jerryz123 force-pushed the dram_on_sbus branch 2 times, most recently from 79263b5 to 6985c53 Compare May 10, 2022 19:14
@jerryz123 jerryz123 merged commit 21de34c into master Sep 14, 2022
@jerryz123 jerryz123 deleted the dram_on_sbus branch September 14, 2022 22:32
sequencer added a commit to sequencer/firesim that referenced this pull request Sep 18, 2022
sequencer added a commit to sequencer/chipyard that referenced this pull request Sep 18, 2022
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2 participants