DCache prioritizes misaligned above guest/page fault

[ingallsj]

Related issue: replaces #2921

Type of change: bug report

Impact: functional change

Development Phase: implementation

Release Notes
PTW fault prioritization: if a PTW doesn't finish with a valid PTE, then we cannot check if the memory address has side effects to take a misaligned exception. So move misaligned fault priority to last.

[sammy17]

Hi, could you please explain what are the side-effects mentioned in this release notes?
Can't we check whether the address is misaligned or not when we only know the address?
Thank you in advance!

[ingallsj]

Hi, could you please explain what are the side-effects mentioned in this release notes?

Memory-Mapped I/O devices can have side-effects when accessed. Some examples:

• setting or clearing a flag in another memory-mapped register location.
• sending or clearing an interrupt.
• flushing a cache block.

Crucially: accesses to memory-mapped I/O devices with side-effects cannot be emulated by splitting them into one-byte-at-a-time accesses.

Can't we check whether the address is misaligned or not when we only know the address?

Yes, we can, but Rocket distinguishes between an emulate-able misaligned access, which takes a misaligned fault for machine mode to emulate it, or a non-emulate-able misaligned access to a side-effect memory address, which takes an access fault to not be emulated.