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TraceGen should observe dmem.ordered when attempting a fence #2779

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Feb 11, 2021
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TraceGen should observe dmem.ordered when attempting a fence #2779

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4 changes: 3 additions & 1 deletion src/main/scala/groundtest/TraceGen.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
val timeout = Bool(OUTPUT)
val mem = new HellaCacheIO
val hartid = UInt(INPUT, log2Up(numGens))
val fence_rdy = Bool(INPUT)
}

val totalNumAddrs = addressBag.size + numExtraAddrs
Expand Down Expand Up @@ -401,7 +402,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
opInProgress := UInt(1)
}
// Wait until all requests have had a response
.elsewhen (reqCount === respCount) {
.elsewhen (reqCount === respCount && io.fence_rdy) {
// Emit fence response
printf("%d: fence-resp @%d\n", tid, cycleCount)
// Move on to a new operation
Expand Down Expand Up @@ -619,6 +620,7 @@ class TraceGenTileModuleImp(outer: TraceGenTile) extends GroundTestTileModuleImp
val dcacheIF = Module(new SimpleHellaCacheIF())
dcacheIF.io.requestor <> tracegen.io.mem
dcache.module.io.cpu <> dcacheIF.io.cache
tracegen.io.fence_rdy := dcache.module.io.cpu.ordered
}

outer.reportCease(Some(tracegen.io.finished))
Expand Down