Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Ignore PAUSE instructions when mcountinhibit.CY=1 #2700

Merged
merged 1 commit into from
Nov 3, 2020
Merged

Ignore PAUSE instructions when mcountinhibit.CY=1 #2700

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions src/main/scala/rocket/CSR.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -227,6 +227,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
val pmp = Vec(nPMPs, new PMP).asOutput
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = UInt(OUTPUT, CSR.nCtr)
val inhibit_cycle = Output(Bool())
val inst = Vec(retireWidth, UInt(width = iLen)).asInput
val trace = Vec(retireWidth, new TracedInstruction).asOutput
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
Expand Down Expand Up @@ -420,6 +421,7 @@ class CSRFile(
val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))

val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
io.inhibit_cycle := reg_mcountinhibit(0)
val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))
else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/rocket/RocketCore.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -853,7 +853,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
io.rocc.cmd.bits.rs2 := wb_reg_rs2

// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || io.dmem.perf.release || take_pc
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false }
io.cease := csr.io.status.cease && !clock_en_reg
io.wfi := csr.io.status.wfi
Expand Down