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Define ResetCrossingType and use with BlockDuringReset in TilePRCIDomain #2641

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merged 33 commits into from
Nov 18, 2020
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11df048
Eschew use of subsystem implicit clock for RTC mixin
davidbiancolin Nov 9, 2020
6ab8120
Eschew use of subsystem implicit clock in BootROM
davidbiancolin Nov 9, 2020
1aed58d
Eschew use of subsystem implicit clock in PLIC + IntBus Wrapper
davidbiancolin Nov 9, 2020
4efa342
Eschew use of subsystem implicit clock in HasPeripheryDebug
davidbiancolin Nov 9, 2020
411ea49
Eschew use of subsystem implicit clock in CLINT
davidbiancolin Nov 9, 2020
9f44dbc
[prci] Provide a require message for ClockGroupAggregator when in.siz…
davidbiancolin Nov 9, 2020
e780995
Have InterruptBusWrapper extend ClockSinkDomain
davidbiancolin Nov 12, 2020
06f39ae
[prci] Provide ibus clock from sbus in BaseSubsystem
davidbiancolin Nov 13, 2020
68ff5ce
Move beu interrupt crossing source register into Tile
ernie-sifive Aug 30, 2020
54bb3e1
Revert "Move beu interrupt crossing source register into Tile"
hcook Sep 8, 2020
dfae384
Revert "Revise trace.valid gating method to relieve timing on reset"
hcook Sep 8, 2020
d90a724
Revert "Use unmodified, possibly async reset for notification ports"
hcook Sep 8, 2020
628a6a6
update BlockDuringReset and add TL and Interrupt versions
hcook Sep 11, 2020
183cdc6
tile: provide reset domain container
hcook Sep 11, 2020
52f3449
prci: alternate clock domain constructors
hcook Sep 11, 2020
533feb0
Expose control over take field for all ClockSinkParameters
jerryz123 Aug 24, 2020
fc557e5
prci: get more aggresive with shouldBeInlined for various adapters an…
hcook Sep 15, 2020
68a92a1
rational crossing: dont BlockDuringReset deq
hcook Sep 16, 2020
0e38f02
interrupts: IntTempNode
hcook Sep 16, 2020
fdecc96
block during reset supports blocking for a stretched amount of cycles
hcook Sep 14, 2020
0f79434
diplomacy: CreditedCrossing implies same clock
hcook Sep 17, 2020
fd84f13
prci: add ResetCrossingType and use with CrossingHelpers to control B…
hcook Sep 17, 2020
aa6e294
Revert "Ensure trace.valid is 0 during async reset"
hcook Sep 17, 2020
1deb82e
util: fix blockduringreset counter to saturate
hcook Sep 17, 2020
5881c82
tile: preserve bind query on slaveNode
hcook Sep 17, 2020
564b15a
diplomacy & prci: adjust crossingtype locations and type hierarchy
hcook Sep 19, 2020
3fac6f7
differentiate ClockCrossingHelpers from ResetCrossingHelpers
hcook Sep 19, 2020
a8d37cf
util: type class implicit Blockable
hcook Sep 26, 2020
8054821
util: BlockableTraceCoreInterface
hcook Sep 28, 2020
2a7cc47
tile: use BundleBridgeBlockDuringReset for tile trace interfaces
hcook Sep 28, 2020
5c6d174
update imports based on scalafix after rebasing
hcook Oct 28, 2020
dab765b
Merge remote-tracking branch 'origin/avoid-subsystem-implicit-clock' …
hcook Nov 13, 2020
d585e68
tile: add backwards compatibility trace broadcast node
hcook Nov 17, 2020
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util: type class implicit Blockable
  • Loading branch information
hcook committed Nov 13, 2020
commit a8d37cf87d9da1fedd74841de2c131a4e4b010df
38 changes: 3 additions & 35 deletions src/main/scala/util/BlockDuringReset.scala
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
package freechips.rocketchip.util

import chisel3._
import chisel3.util.{Counter, DecoupledIO, RegEnable}
import chisel3.util.{Counter, RegEnable}

/** Blocks transactions until the cycle after reset. */
object BlockDuringReset
@@ -13,39 +13,7 @@ object BlockDuringReset
case i => RegEnable(true.B, false.B, Counter(true.B, i)._2)
}

def apply[T <: Data](enq: DecoupledIO[T], stretchCycles: Int = 0): DecoupledIO[T] = {
val out_of_reset = outOfReset(stretchCycles)
val res = Wire(enq.cloneType)
res.valid := enq.valid
enq.ready := res.ready
res.bits := enq.bits
when (!out_of_reset) {
res.valid := false.B
enq.ready := false.B
}
res
}

def apply(valid: Bool, stretchCycles: Int): Bool = {
val out_of_reset = outOfReset(stretchCycles)
valid && out_of_reset
}

def apply[T <: DataCanBeValid](data: T, stretchCycles: Int): T = {
val out_of_reset = outOfReset(stretchCycles)
val res = Wire(data.cloneType)
res := data
res.valid := data.valid && out_of_reset
res
}

def apply[T <: DataCanBeValid](data: Vec[T], stretchCycles: Int): Vec[T] = {
val out_of_reset = outOfReset(stretchCycles)
val res = Wire(data.cloneType)
res.zip(data)foreach { case (r, d) =>
r := d
r.valid := d.valid && out_of_reset
}
res
def apply[T <: Data : Blockable](data: T, stretchCycles: Int = 0): T = {
implicitly[Blockable[T]].blockWhile(!outOfReset(stretchCycles), data)
}
}
48 changes: 48 additions & 0 deletions src/main/scala/util/Blockable.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
// See LICENSE.SiFive for license details.

package freechips.rocketchip.util

import chisel3._
import chisel3.util.DecoupledIO

/** A trait supplying a function allowing the contents of data
* to be supressed for a time period, i.e. be blocked.
*/
trait Blockable[T <: Data] {
def blockWhile(enable_blocking: Bool, data: T): T
}

object Blockable {
implicit object BlockableBool extends Blockable[Bool] {
def blockWhile(enable_blocking: Bool, x: Bool): Bool = x && !enable_blocking
}

implicit def BlockableDataCanBeValid[T <: DataCanBeValid]: Blockable[T] = new Blockable[T] {
def blockWhile(enable_blocking: Bool, data: T): T = {
val blocked: T = Wire(chiselTypeOf(data))
blocked := data
when (enable_blocking) { blocked.valid := false.B }
blocked
}
}

implicit def BlockableDecoupled[T <: Data]: Blockable[DecoupledIO[T]] = new Blockable[DecoupledIO[T]] {
def blockWhile(enable_blocking: Bool, data: DecoupledIO[T]): DecoupledIO[T] = {
val res = Wire(chiselTypeOf(data))
res.valid := data.valid
data.ready := res.ready
res.bits := data.bits
when (enable_blocking) {
res.valid := false.B
data.ready := false.B
}
res
}
}

implicit def BlockableVec[T <: Data : Blockable]: Blockable[Vec[T]] = new Blockable[Vec[T]] {
def blockWhile(enable_blocking: Bool, data: Vec[T]): Vec[T] = {
VecInit(data.map(x => implicitly[Blockable[T]].blockWhile(enable_blocking, x)))
}
}
}