Chisel compile warning: Chisel3 packages imports

src/main/scala/amba/ahb/Monitor.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.amba.ahb
 
 import chisel3._
-import chisel3.core.Reset
 import freechips.rocketchip.config.Parameters
 
 case class AHBSlaveMonitorArgs(edge: AHBEdgeParameters)

src/main/scala/devices/debug/Periphery.scala

@@ -3,7 +3,7 @@
 package freechips.rocketchip.devices.debug
 
 import chisel3._
-import chisel3.core.IntParam
+import chisel3.experimental.IntParam
 import chisel3.util._
 import chisel3.util.HasBlackBoxResource
 import freechips.rocketchip.config.{Field, Parameters}

src/main/scala/diplomacy/BundleBridge.scala

@@ -4,8 +4,7 @@ package freechips.rocketchip.diplomacy
 
 import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.core.{DataMirror,ActualDirection}
-import chisel3.experimental.IO
+import chisel3.experimental.{DataMirror,IO}
 import freechips.rocketchip.config.{Parameters,Field}
 
 case class BundleBridgeParams[T <: Data](gen: () => T)

src/main/scala/prci/ResetWrangler.scala

@@ -3,7 +3,6 @@ package freechips.rocketchip.prci
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._

src/main/scala/prci/TestClockSource.scala

@@ -2,6 +2,7 @@ package freechips.rocketchip.prci
 
 import chisel3._
 import chisel3.util.HasBlackBoxInline
+import chisel3.experimental.DoubleParam
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 
@@ -13,7 +14,7 @@ class ClockSourceIO extends Bundle {
 
 /** This clock source is only intended to be used in test harnesses, and does not work correctly in verilator. */
 class ClockSourceAtFreq(val freqMHz: Double) extends BlackBox(Map(
-  "PERIOD_PS" -> core.DoubleParam(1000000/freqMHz)
+  "PERIOD_PS" -> DoubleParam(1000000/freqMHz)
 )) with HasBlackBoxInline {
   val io = IO(new ClockSourceIO)
 

src/main/scala/rocket/CSR.scala

@@ -5,7 +5,7 @@ package freechips.rocketchip.rocket
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import chisel3.experimental._
+import chisel3.withClock
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._

src/main/scala/rocket/Frontend.scala

@@ -5,16 +5,17 @@ package freechips.rocketchip.rocket
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import chisel3.experimental._
+import chisel3.{withClock,withReset}
+import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.chiselName
 import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
-import chisel3.internal.sourceinfo.SourceInfo
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{ICacheLogicalTreeNode}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.ICacheLogicalTreeNode
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
   val pc = UInt(width = vaddrBitsExtended)

src/main/scala/rocket/PTW.scala

@@ -5,14 +5,15 @@ package freechips.rocketchip.rocket
 
 import Chisel._
 import Chisel.ImplicitConversions._
+import chisel3.withClock
+import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.chiselName
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.subsystem.CacheBlockBytes
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
-import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.experimental._
 import scala.collection.mutable.ListBuffer
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/RocketCore.scala

@@ -5,7 +5,8 @@ package freechips.rocketchip.rocket
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import chisel3.experimental._
+import chisel3.withClock
+import chisel3.experimental.chiselName
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._

src/main/scala/tile/FPU.scala

@@ -5,14 +5,14 @@ package freechips.rocketchip.tile
 
 import Chisel._
 import Chisel.ImplicitConversions._
-
+import chisel3.withClock
+import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.chiselName
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.rocket.Instructions._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
-import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.experimental._
 
 case class FPUParams(
   fLen: Int = 64,

src/main/scala/tilelink/Monitor.scala

@@ -4,13 +4,12 @@ package freechips.rocketchip.tilelink
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.Reset
 import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
+import chisel3.experimental.chiselName
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.{HeterogeneousBag, PlusArg}
 import freechips.rocketchip.formal._
-import chisel3.experimental.chiselName
 
 case class TLMonitorArgs(edge: TLEdge)
 

src/main/scala/util/Annotations.scala

@@ -172,7 +172,7 @@ trait DontTouch { self: RawModule =>
   // TODO: this is a workaround for firrtl #756
   def dontTouch(data: Data): Unit = data match {
      case agg: Aggregate => agg.getElements.foreach(dontTouch)
-     case elt: Element => chisel3.core.dontTouch(elt)
+     case elt: Element => chisel3.dontTouch(elt)
   }
 
   /** Marks every port as don't touch

src/main/scala/util/DescribedSRAM.scala

@@ -4,14 +4,12 @@
 package freechips.rocketchip.util
 
 import chisel3.internal.InstanceId
-import freechips.rocketchip.util.Annotated
-import freechips.rocketchip.diplomacy.DiplomaticSRAM
 import chisel3.{Data, SyncReadMem, Vec}
 import chisel3.util.log2Ceil
 import freechips.rocketchip.amba.axi4.AXI4RAM
+import freechips.rocketchip.diplomacy.DiplomaticSRAM
 import freechips.rocketchip.diplomaticobjectmodel.DiplomaticObjectModelAddressing
 import freechips.rocketchip.diplomaticobjectmodel.model.{OMSRAM, OMRTLModule}
-
 import scala.math.log10
 
 object DescribedSRAM {

src/main/scala/util/HeterogeneousBag.scala

@@ -3,7 +3,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.core.Record
+import chisel3.Record
 import scala.collection.immutable.ListMap
 
 final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with collection.IndexedSeq[T] {

src/main/scala/util/ResetCatchAndSync.scala

@@ -3,7 +3,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.experimental.{withClockAndReset, withReset}
+import chisel3.{withClockAndReset, withReset}
 
 /** Reset: asynchronous assert,
   *  synchronous de-assert