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Qualify load and store watchpoints by instruction type #2317

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merged 1 commit into from
Mar 3, 2020
Merged

Qualify load and store watchpoints by instruction type #2317

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10 changes: 6 additions & 4 deletions src/main/scala/rocket/Breakpoint.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,8 @@ class BP(implicit p: Parameters) extends CoreBundle()(p) {

class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val dvalid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
Expand Down Expand Up @@ -87,11 +88,12 @@ class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with Has

bpw.action := action
bpw.valid(0) := false.B
bpw.dvalid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B

when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.dvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.dvalid(0) := true.B }
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }

(end || r, end || w, end || x)
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/RocketCore.scala
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Expand Up @@ -595,7 +595,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
wb_reg_raw_inst := mem_reg_raw_inst
wb_reg_mem_size := mem_reg_mem_size
wb_reg_pc := mem_reg_pc
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => bpw.dvalid(0) }
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }

}

Expand Down