separate generator behavior into phases

Makefrag

@@ -6,9 +6,14 @@ endif
 MODEL ?= TestHarness
 PROJECT ?= freechips.rocketchip.system
 CFG_PROJECT ?= $(PROJECT)
-CONFIG ?= DefaultConfig
+CONFIG ?= $(CFG_PROJECT).DefaultConfig
 # TODO: For now must match rocketchip.Generator
-long_name = $(PROJECT).$(CONFIG)
+comma := ,
+space := $() $()
+splitConfigs := $(subst $(comma), ,$(CONFIG))
+configBases := $(foreach config,$(splitConfigs),$(lastword $(subst ., ,$(config))))
+CONFIG_STR := $(subst $(space),_,$(configBases))
+long_name = $(PROJECT).$(CONFIG_STR)
 
 VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
 

emulator/Makefrag-verilator

@@ -10,7 +10,7 @@ verilog = \
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG)"
 
 %.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
@@ -69,7 +69,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
   --threads $(VERILATOR_THREADS) -Wno-UNOPTTHREADS \
 	-Wno-STMTDLY --x-assign unique \
   -I$(vsrc) \
-  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(csrc)/verilator.h -include $(generated_dir)/$(PROJECT).$(CONFIG).plusArgs"
+  -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(csrc)/verilator.h -include $(generated_dir)/$(long_name).plusArgs"
 cppfiles = $(addprefix $(csrc)/, $(addsuffix .cc, $(CXXSRCS)))
 headers = $(wildcard $(csrc)/*.h)
 

regression/Makefile

@@ -46,36 +46,36 @@ endif
 
 ifeq ($(SUITE),RocketSuiteA)
 PROJECT=freechips.rocketchip.system
-CONFIGS=DefaultConfig
+CONFIGS=$(PROJECT).DefaultConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteB)
 PROJECT=freechips.rocketchip.system
-CONFIGS=DefaultBufferlessConfig
+CONFIGS=$(PROJECT).DefaultBufferlessConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteC)
 PROJECT=freechips.rocketchip.system
-CONFIGS=TinyConfig
+CONFIGS=$(PROJECT).TinyConfig
 endif
 
 ifeq ($(SUITE),UnittestSuite)
 PROJECT=freechips.rocketchip.unittest
-CONFIGS=AMBAUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
+CONFIGS=$(PROJECT).AMBAUnitTestConfig $(PROJECT).TLSimpleUnitTestConfig $(PROJECT).TLWidthUnitTestConfig
 endif
 
 ifeq ($(SUITE), JtagDtmSuite)
 PROJECT=freechips.rocketchip.system
 
 export JTAG_DTM_ENABLE_SBA ?= off
 ifeq ($(JTAG_DTM_ENABLE_SBA), off)
-CONFIGS_32=WithJtagDTMSystem_DefaultRV32Config
-CONFIGS_64=WithJtagDTMSystem_DefaultConfig
+CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultRV32Config
+CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultConfig
 endif
 
 ifeq ($(JTAG_DTM_ENABLE_SBA), on)
-CONFIGS_32=WithJtagDTMSystem_WithDebugSBASystem_DefaultRV32Config
-CONFIGS_64=WithJtagDTMSystem_WithDebugSBASystem_DefaultConfig
+CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultRV32Config
+CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultConfig
 endif
 
 CONFIGS += $(CONFIGS_32)
@@ -89,18 +89,18 @@ endif
 ifeq ($(SUITE), Miscellaneous)
 PROJECT=freechips.rocketchip.system
 CONFIGS=\
-	DefaultSmallConfig \
-	DualBankConfig \
-	DualChannelConfig \
-	DualChannelDualBankConfig \
-	RoccExampleConfig \
-	Edge128BitConfig \
-	Edge32BitConfig \
-	QuadChannelBenchmarkConfig \
-	EightChannelConfig \
-	DualCoreConfig \
-	MemPortOnlyConfig \
-	MMIOPortOnlyConfig
+	$(PROJECT).DefaultSmallConfig \
+	$(PROJECT).DualBankConfig \
+	$(PROJECT).DualChannelConfig \
+	$(PROJECT).DualChannelDualBankConfig \
+	$(PROJECT).RoccExampleConfig \
+	$(PROJECT).Edge128BitConfig \
+	$(PROJECT).Edge32BitConfig \
+	$(PROJECT).QuadChannelBenchmarkConfig \
+	$(PROJECT).EightChannelConfig \
+	$(PROJECT).DualCoreConfig \
+	$(PROJECT).MemPortOnlyConfig \
+	$(PROJECT).MMIOPortOnlyConfig
 endif
 
 # These are the named regression targets.  While it's expected you run them in

src/main/scala/groundtest/Generator.scala

@@ -2,11 +2,7 @@
 
 package freechips.rocketchip.groundtest
 
-import freechips.rocketchip.util.GeneratorApp
+import firrtl.options.StageMain
+import freechips.rocketchip.system.RocketChipStage
 
-object Generator extends GeneratorApp {
-  generateFirrtl
-  generateAnno
-  generateTestSuiteMakefrags // TODO: Needed only for legacy make targets
-  generateArtefacts
-}
+object Generator extends StageMain(new RocketChipStage)

src/main/scala/stage/RocketChipAnnotations.scala

@@ -0,0 +1,52 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.stage
+
+import chisel3.experimental.BaseModule
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{HasShellOptions, ShellOption, Unserializable}
+
+sealed trait RocketChipOption extends Unserializable { this: Annotation => }
+
+/* required options */
+
+/** Path to top module class */
+case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with RocketChipOption
+private[stage] object TopModuleAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "top-module",
+      toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])),
+      helpText = "<top module>",
+      shortOption = Some("T")
+    )
+  )
+}
+
+/** Paths to config classes */
+case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with RocketChipOption
+private[stage] object ConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Seq[String]](
+      longOption = "configs",
+      toAnnotationSeq = a => Seq(ConfigsAnnotation(a)),
+      helpText = "<comma-delimited configs>",
+      shortOption = Some("C")
+    )
+  )
+}
+
+/* optional options */
+
+/** Optional base name for generated files' filenames */
+case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with RocketChipOption
+private[stage] object OutputBaseNameAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "name",
+      toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)),
+      helpText = "<base name of output files>",
+      shortOption = Some("n")
+    )
+  )
+}

src/main/scala/stage/RocketChipCli.scala

@@ -0,0 +1,17 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.stage
+
+import firrtl.options.Shell
+
+trait RocketChipCli { this: Shell =>
+
+  parser.note("Rocket Chip Compiler Options")
+  Seq(
+    TopModuleAnnotation,
+    ConfigsAnnotation,
+    OutputBaseNameAnnotation,
+  )
+    .foreach(_.addOptions(parser))
+
+}

src/main/scala/stage/RocketChipOptions.scala

@@ -0,0 +1,41 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.stage
+
+class RocketChipOptions private[stage] (
+                                         val topModule:         Option[Class[_ <: Any]] = None,
+                                         val configNames:       Option[Seq[String]] = None,
+                                         val outputBaseName:    Option[String] = None) {
+
+  private[stage] def copy(
+                           topModule:         Option[Class[_ <: Any]] = topModule,
+                           configNames:       Option[Seq[String]] = configNames,
+                           outputBaseName:    Option[String] = outputBaseName,
+                         ): RocketChipOptions = {
+
+    new RocketChipOptions(
+      topModule=topModule,
+      configNames=configNames,
+      outputBaseName=outputBaseName,
+    )
+  }
+
+  lazy val topPackage: Option[String] = topModule match {
+    case Some(a) => Some(a.getPackage.getName)
+    case _ => None
+  }
+
+  lazy val configClass: Option[String] = configNames match {
+    case Some(names) =>
+      val classNames = names.map{ n => n.split('.').last }
+      Some(classNames.mkString("_"))
+    case _ => None
+  }
+
+  lazy val longName: Option[String] = outputBaseName match {
+    case Some(name) => Some(name)
+    case _ =>
+      if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
+  }
+}
+

src/main/scala/stage/package.scala

@@ -0,0 +1,24 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip
+
+import firrtl.AnnotationSeq
+import firrtl.options.OptionsView
+
+package object stage {
+
+  implicit object RocketChipOptionsView extends OptionsView[RocketChipOptions] {
+
+    def view(annotations: AnnotationSeq): RocketChipOptions = annotations
+      .collect { case a: RocketChipOption => a }
+      .foldLeft(new RocketChipOptions()){ (c, x) =>
+        x match {
+          case TopModuleAnnotation(a)         => c.copy(topModule = Some(a))
+          case ConfigsAnnotation(a)           => c.copy(configNames = Some(a))
+          case OutputBaseNameAnnotation(a)    => c.copy(outputBaseName = Some(a))
+        }
+      }
+
+  }
+
+}