Reduce size of Bypass logic in debug modoule

Parameterize atomics and transferSize in TLBusBypassBase, set in dmOuterAsync

Bus Blocker: BriskBusBlocker is very similar to TLBusBlocker

DMI Bus Blocker: clean up API for error device buffering

Debug: reduce hardware added to TLError on APB interface

Update Zero.scala

Correct the minLatency for TLZero back to 1

Debug: fix rebase issue

Debug: revert unncessary whitespace change

Add optional buffering for C channel as well in error

BusBypass: correct removal of sync reset reliance

…mal and bypass device, otherwise you can get assertion failures when using the bypass path

fix bad merge

Parameters: fix bad merge

regression: FESVR is now part of spike so don't build it

bump riscv-tools for FESVR DMACTIVE fix

Rocket-tools: remove prolematic space

rocket-tools: bumping to use latest-ish versions of tools and FSF GDB

rocket-tools: bump hash and build the FSF GDB, not riscv GDB

Regression: apparently need to have the binutils-gdb submodule even if we don't plan to comiple it

Travis: bump pexpect since gdbserver.py now uses Python3

Debug tests: now need to be python3 compatible

dmactive: bump riscv-tools hash

Debug regressions: need to add RISCV/bin to the path now apparently

…e limit

…ocker