Merge pull request #2842 from jerryz123/patch-3

Allow forcing RocketTiles into independent PRCI group
chipsalliance · Apr 24, 2022 · edc8d40 · edc8d40
2 parents 4fc4350 + a6906b8
commit edc8d40
Showing 1 changed file with 3 additions and 4 deletions.
diff --git a/src/main/scala/subsystem/RocketSubsystem.scala b/src/main/scala/subsystem/RocketSubsystem.scala
@@ -12,10 +12,9 @@ case class RocketCrossingParams(
   master: TilePortParamsLike = TileMasterPortParams(),
   slave: TileSlavePortParams = TileSlavePortParams(),
   mmioBaseAddressPrefixWhere: TLBusWrapperLocation = CBUS,
-  resetCrossingType: ResetCrossingType = NoResetCrossing()
-) extends TileCrossingParamsLike {
-  def forceSeparateClockReset: Boolean = false
-}
+  resetCrossingType: ResetCrossingType = NoResetCrossing(),
+  forceSeparateClockReset: Boolean = false
+) extends TileCrossingParamsLike
 
 case class RocketTileAttachParams(
   tileParams: RocketTileParams,