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cleaning up test generation
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@debs-sifive
debs-sifive committed Feb 11, 2020
1 parent 034614f commit db5bb87
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Showing 3 changed files with 25 additions and 118 deletions.
15 changes: 12 additions & 3 deletions src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,9 +7,11 @@ import firrtl.AnnotationSeq
import firrtl.options.{Phase, PreservesAll, StageOptions}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.system.TestGeneration
import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
import freechips.rocketchip.util.HasRocketChipStageUtils

case class RocketTestSuiteAnnotation(suite: RocketTestSuite)

class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {

override val prerequisites = Seq(classOf[Checks], classOf[Elaborate])
Expand All @@ -18,8 +20,15 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has
val targetDir = view[StageOptions](annotations).targetDir
val fileName = s"${view[RocketChipOptions](annotations).longName}.d"

addTestSuites(annotations)
writeOutputFile(targetDir, fileName, TestGeneration.generateMakefrag)
//addTestSuites(annotations)
//writeOutputFile(targetDir, fileName, TestGeneration.generateMakefrag)
val makefrag =
annotations
.collect{ case a: RocketTestSuiteAnnotation => a.suite }
.groupBy(_.kind)
.map { case (kind, s) => TestGeneration.gen(kind, s) }
.mkString("\n")
writeOutputFile(targetDir, fileName, makefrag)

annotations
}
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26 changes: 13 additions & 13 deletions src/main/scala/system/RocketTestSuite.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -61,16 +61,15 @@ object TestGeneration {

def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }

def generateMakefrag: String = {
def gen(kind: String, s: Seq[RocketTestSuite]) = {
if(s.length > 0) {
val envs = s.groupBy(_.envName)
val targets = s.map(t => s"$$(${t.makeTargetName})").mkString(" ")
s.map(_.toString).mkString("\n") +
envs.filterKeys(_ != "").map( {
case (env,envsuites) => {
val suites = envsuites.map(t => s"$$(${t.makeTargetName})").mkString(" ")
s"""
private[rocketchip] def gen(kind: String, s: Seq[RocketTestSuite]) = {
if(s.length > 0) {
val envs = s.groupBy(_.envName)
val targets = s.map(t => s"$$(${t.makeTargetName})").mkString(" ")
s.map(_.toString).mkString("\n") +
envs.filterKeys(_ != "").map( {
case (env,envsuites) => {
val suites = envsuites.map(t => s"$$(${t.makeTargetName})").mkString(" ")
s"""
run-$kind-$env-tests: $$(addprefix $$(output_dir)/, $$(addsuffix .out, $suites))
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED):(.*)/i )' $$^ /dev/null | perl -pe 'BEGIN { $$$$failed = 0 } $$$$failed = 1 if(/FAILED/i); END { exit($$$$failed) }'
run-$kind-$env-tests-debug: $$(addprefix $$(output_dir)/, $$(addsuffix .vpd, $suites))
Expand All @@ -89,17 +88,18 @@ run-$kind-tests-fst: $$(addprefix $$(output_dir)/, $$(addsuffix .fst, $targets))
run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets))
\t@echo; perl -ne 'print " [$$$$1] $$$$ARGV \\t$$$$2\\n" if( /\\*{3}(.{8})\\*{3}(.*)/ || /ASSERTION (FAILED):(.*)/i )' $$^ /dev/null | perl -pe 'BEGIN { $$$$failed = 0 } $$$$failed = 1 if(/FAILED/i); END { exit($$$$failed) }'
"""
} else { "\n" }
}
} else { "\n" }
}

def generateMakeFrag: String = {
suites.values.toSeq.groupBy(_.kind).map { case (kind, s) => gen(kind, s) }.mkString("\n")
}

}

object DefaultTestSuites {
val rv32uiNames = LinkedHashSet(
"simple", "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", "bltu", "bne", "fence_i",
"simple", "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", "bltu", "bne", "fence_i",
"jal", "jalr", "lb", "lbu", "lh", "lhu", "lui", "lw", "or", "ori", "sb", "sh", "sw", "sll", "slli",
"slt", "slti", "sra", "srai", "srl", "srli", "sub", "xor", "xori")
val rv32ui = new AssemblyTestSuite("rv32ui", rv32uiNames)(_)
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102 changes: 0 additions & 102 deletions src/main/scala/util/GeneratorUtils.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,14 +7,6 @@ import java.io.{File, FileWriter}
import Chisel.throwException
import chipsalliance.rocketchip.config.{Config, Parameters}
import chisel3.internal.firrtl.Circuit
import firrtl.options.Viewer.view
import firrtl.AnnotationSeq
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.system.{DefaultTestSuites, RegressionTestSuite, TestGeneration}
import freechips.rocketchip.tile.XLen

import scala.collection.mutable.LinkedHashSet

trait HasRocketChipStageUtils {

Expand Down Expand Up @@ -53,100 +45,6 @@ trait HasRocketChipStageUtils {
f
}

/** Output software test Makefrags, which provide targets for integration testing. */
def addTestSuites(annotations: AnnotationSeq) {
import DefaultTestSuites._
val rOpts = view[RocketChipOptions](annotations)
val params = getConfig(rOpts.configNames.get).toInstance
val xlen = params(XLen)

val regressionTests = LinkedHashSet(
"rv64ud-v-fcvt",
"rv64ud-p-fdiv",
"rv64ud-v-fadd",
"rv64uf-v-fadd",
"rv64um-v-mul",
"rv64mi-p-breakpoint",
"rv64uc-v-rvc",
"rv64ud-v-structural",
"rv64si-p-wfi",
"rv64um-v-divw",
"rv64ua-v-lrsc",
"rv64ui-v-fence_i",
"rv64ud-v-fcvt_w",
"rv64uf-v-fmin",
"rv64ui-v-sb",
"rv64ua-v-amomax_d",
"rv64ud-v-move",
"rv64ud-v-fclass",
"rv64ua-v-amoand_d",
"rv64ua-v-amoxor_d",
"rv64si-p-sbreak",
"rv64ud-v-fmadd",
"rv64uf-v-ldst",
"rv64um-v-mulh",
"rv64si-p-dirty",
"rv32mi-p-ma_addr",
"rv32mi-p-csr",
"rv32ui-p-sh",
"rv32ui-p-lh",
"rv32uc-p-rvc",
"rv32mi-p-sbreak",
"rv32ui-p-sll")

// TODO: for now only generate tests for the first core in the first subsystem
params(RocketTilesKey).headOption.map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)

TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)

/* Filter the regression tests based on what the Rocket Chip configuration supports */
val extensions = {
val fd = coreParams.fpu.map {
case cfg if cfg.fLen >= 64 => "fd"
case _ => "f"
}
val m = coreParams.mulDiv.map{ case _ => "m" }
fd ++ m ++ Seq( if (coreParams.useRVE) Some("e") else Some("i"),
if (coreParams.useAtomics) Some("a") else None,
if (coreParams.useCompressed) Some("c") else None )
.flatten
.mkString("")
}
val re = s"""^rv$xlen[usm][$extensions].+""".r
regressionTests.retain{
case re() => true
case _ => false
}
TestGeneration.addSuite(new RegressionTestSuite(regressionTests))
}
}
}

object ElaborationArtefacts {
Expand Down

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