Merge pull request #2610 from chipsalliance/clockdivider-fix

bug fix for ClockDivider
chipsalliance · Aug 24, 2020 · d6a5dc3 · d6a5dc3
2 parents 6f0cf54 + d06c9ee
commit d6a5dc3
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/prci/ClockDivider.scala b/src/main/scala/prci/ClockDivider.scala
@@ -11,8 +11,8 @@ import freechips.rocketchip.util.{ClockDivider3, Pow2ClockDivider}
 */
 class ClockDivider(div: Int)(implicit p: Parameters) extends LazyModule {
   val node = ClockAdapterNode(
-    sourceFn = { case src => src.copy(give = src.give.map(x => x.copy(freqMHz = x.freqMHz / 2))) },
-    sinkFn   = { case snk => snk.copy(take = snk.take.map(x => x.copy(freqMHz = x.freqMHz * 2))) })
+    sourceFn = { case src => src.copy(give = src.give.map(x => x.copy(freqMHz = x.freqMHz / div))) },
+    sinkFn   = { case snk => snk.copy(take = snk.take.map(x => x.copy(freqMHz = x.freqMHz * div))) })
 
   lazy val module = new LazyModuleImp(this) {
     (node.in zip node.out).foreach { case ((in, _), (out, _)) =>