Add b-ext tests to CI

chipsalliance · Aug 12, 2024 · b62bdef · b62bdef
1 parent 09bbf5c
commit b62bdef
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Showing 4 changed files with 15 additions and 3 deletions.
diff --git a/.github/workflows/mill-ci.yml b/.github/workflows/mill-ci.yml
@@ -25,7 +25,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config]
+        config: [DefaultConfig, DefaultBufferlessConfig, DefaultRV32Config, TinyConfig, DefaultFP16Config, DefaultBConfig, DefaultRV32BConfig]
     steps:
       - uses: actions/checkout@v2
         with:

diff --git a/build.sc b/build.sc
@@ -316,6 +316,7 @@ object emulator extends Cross[Emulator](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBufferlessConfig"),
   // RocketSuiteC
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig"),
+
   // Unittest
   ("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.AMBAUnitTestConfig"),
   ("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.TLSimpleUnitTestConfig"),
@@ -343,6 +344,9 @@ object emulator extends Cross[Emulator](
   //
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig"),
+
 )
 
 object `runnable-riscv-test` extends mill.Cross[RiscvTest](
@@ -422,6 +426,12 @@ object `runnable-riscv-test` extends mill.Cross[RiscvTest](
 
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-p", "none"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-v", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzba-p", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzbb-p", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBConfig", "rv64uzbs-p", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzba-p", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzbb-p", "none"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32BConfig", "rv32uzbs-p", "none"),
 )
 
 object `runnable-arch-test` extends mill.Cross[ArchTest](

diff --git a/overlay.nix b/overlay.nix
@@ -8,7 +8,7 @@ final: prev: {
   });
   riscvTests = final.pkgsCross.riscv64-embedded.stdenv.mkDerivation rec {
     pname = "riscv-tests";
-    version = "55bbcc8c06637a31cc01970881ba8072838a9121";
+    version = "f2f748ebb9cf8ea049103f85c4cbf7e8a2927b16";
     src = final.fetchgit {
       url = "https://github.com/riscv-software-src/riscv-tests.git";
       rev = "${version}";

diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
@@ -5,7 +5,7 @@ package freechips.rocketchip.system
 
 import org.chipsalliance.cde.config.Config
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHypervisor, With1TinyCore, WithScratchpadsOnly, WithCloneRocketTiles}
+import freechips.rocketchip.rocket.{WithNBigCores, WithNMedCores, WithNSmallCores, WithRV32, WithFP16, WithHypervisor, With1TinyCore, WithScratchpadsOnly, WithCloneRocketTiles, WithB}
 
 class WithJtagDTMSystem extends freechips.rocketchip.subsystem.WithJtagDTM
 class WithDebugSBASystem extends freechips.rocketchip.subsystem.WithDebugSBA
@@ -27,6 +27,8 @@ class DefaultBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ n
 class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new WithCoherentBusTopology ++ new BaseConfig)
 class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
 class DefaultFP16Config extends Config(new WithFP16 ++ new DefaultConfig)
+class DefaultBConfig extends Config(new WithB ++ new DefaultConfig)
+class DefaultRV32BConfig extends Config(new WithB ++ new DefaultRV32Config)
 
 class HypervisorConfig extends Config(new WithHypervisor ++ new DefaultConfig)