Update DMI.scala

chipsalliance · Jul 17, 2020 · afad0d8 · afad0d8
1 parent d11c923
commit afad0d8
Showing 1 changed file with 6 additions and 4 deletions.
diff --git a/src/main/scala/devices/debug/DMI.scala b/src/main/scala/devices/debug/DMI.scala
@@ -79,10 +79,12 @@ class ClockedDMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p){
   */
 
 class DMIToTL(implicit p: Parameters) extends LazyModule {
-  val node = TLClientNode(Seq(TLMasterPortParameters.v2(Seq(TLMasterParameters.v2(name = "debug",
-                                                                                  emits = TLMasterToSlaveTransferSizes(get = TransferSizes(4,4),
-                                                                                                                       putFull = TransferSizes(4,4),
-                                                                                                                       putPartial = TransferSizes(4,4)))))))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v2(Seq(TLMasterParameters.v2(
+    name = "debug",
+    emits = TLMasterToSlaveTransferSizes(
+      get = TransferSizes(4,4),
+      putFull = TransferSizes(4,4),
+      putPartial = TransferSizes(4,4)))))))
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {