Merge pull request #2434 from chipsalliance/OM_Sv48

Object Model: add Sv48 to RocketISA addressTranslationModes
chipsalliance · Apr 25, 2020 · 9002625 · 9002625
2 parents 05ea095 + 2e3f15b
commit 9002625
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Showing 4 changed files with 11 additions and 9 deletions.
diff --git a/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala b/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala
@@ -60,7 +60,8 @@ class ICacheLogicalTreeNode(icache: ICache, deviceOpt: Option[SimpleDevice], par
 
 class RocketLogicalTreeNode(
   tile: RocketTile,
-  XLen: Int
+  XLen: Int,
+  PgLevels: Int
 ) extends LogicalTreeNode(() => Some(tile.cpuDevice)) {
 
   def getOMInterruptTargets(): Seq[OMInterruptTarget] = {
@@ -83,7 +84,7 @@ class RocketLogicalTreeNode(
     val omBusError = components.collectFirst { case x: OMBusError => x }
 
     Seq(OMRocketCore(
-      isa = OMISA.rocketISA(tile, XLen),
+      isa = OMISA.rocketISA(tile, XLen, PgLevels),
       mulDiv =  coreParams.mulDiv.map{ md => OMMulDiv.makeOMI(md, XLen)},
       fpu = coreParams.fpu.map{f => OMFPU(fLen = f.fLen)},
       performanceMonitor = PerformanceMonitor.perfmon(coreParams),

diff --git a/src/main/scala/diplomaticobjectmodel/model/OMISA.scala b/src/main/scala/diplomaticobjectmodel/model/OMISA.scala
@@ -56,7 +56,7 @@ case class OMVectorExtension(
 )
 
 object OMISA {
-  def rocketISA(tile: RocketTile, xLen: Int): OMISA = {
+  def rocketISA(tile: RocketTile, xLen: Int, pgLevels: Int): OMISA = {
     val coreParams = tile.rocketParams.core
 
     val baseInstructionSet = xLen match {
@@ -82,10 +82,11 @@ object OMISA {
     }
 
     val addressTranslationModes = xLen match {
-        case _ if !coreParams.useVM => Bare
-        case 32 => Sv32
-        case 64 => Sv39
-        case _ => throw new IllegalArgumentException(s"ERROR: Invalid Xlen: $xLen")
+      case _ if !coreParams.useVM => Bare
+      case 32 if (pgLevels == 2) => Sv32
+      case 64 if (pgLevels == 3) => Sv39
+      case 64 if (pgLevels == 4) => Sv48
+      case _ => throw new IllegalArgumentException(s"ERROR: Invalid Xlen/PgLevels combination: $xLen/$pgLevels")
     }
 
     OMISA(

diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
@@ -153,7 +153,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
     Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
   }
   val fragmented_superpage_ppn = {
-    val choices = (pgLevels-1 until 0 by -1).map(i => Cat(r_pte.ppn >> (pgLevelBits*i), r_req.addr(pgLevelBits*i-1, 0)))
+    val choices = (pgLevels-1 until 0 by -1).map(i => Cat(r_pte.ppn >> (pgLevelBits*i), r_req.addr(((pgLevelBits*i) min vpnBits)-1, 0).padTo(pgLevelBits*i)))
     choices(count)
   }
 

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
@@ -51,7 +51,7 @@ class RocketTile private(
   val slaveNode = TLIdentityNode()
   val masterNode = visibilityNode
 
-  val rocketLogicalTree = new RocketLogicalTreeNode(this, p(XLen))
+  val rocketLogicalTree = new RocketLogicalTreeNode(this, p(XLen), pgLevels)
 
   val dtim_adapter = tileParams.dcache.flatMap { d => d.scratch.map { s =>
     val coreParams = {