[DO NOT MERGE] tmp workaround over riscv/riscv-opcodes#111

chipsalliance · May 3, 2022 · 8e23368 · 8e23368
1 parent 59fc78a
commit 8e23368
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala
@@ -561,6 +561,9 @@ object Instructions {
   def SLL16              = BitPat("b0101010??????????000?????1110111")
   def SLL32              = BitPat("b0101010??????????010?????1110111")
   def SLL8               = BitPat("b0101110??????????000?????1110111")
+  def SLLI_RV32          = BitPat("b0000000??????????001?????0010011")
+  def SRLI_RV32          = BitPat("b0000000??????????101?????0010011")
+  def SRAI_RV32          = BitPat("b0100000??????????101?????0010011")
   def SLLI               = BitPat("b000000???????????001?????0010011")
   def SLLI16             = BitPat("b01110100?????????000?????1110111")
   def SLLI32             = BitPat("b0111010??????????010?????1110111")