Add tlb_port to NBDcache as well

src/main/scala/groundtest/Tile.scala

@@ -43,10 +43,7 @@ abstract class GroundTestTile(
   dcacheOpt.foreach { m =>
     m.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode }
     InModuleBody {
-      m.module match {
-        case module: DCacheModule => module.tlb_port := DontCare
-        case other => other
-      }
+      m.module.io.tlb_port := DontCare
     }
   }
 

src/main/scala/rocket/DCache.scala

@@ -91,8 +91,6 @@ class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) {
 }
 
 class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
-  val tlb_port = IO(new DCacheTLBPort)
-
   val tECC = cacheParams.tagCode
   val dECC = cacheParams.dataCode
   require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits")
@@ -179,7 +177,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s1_nack = WireDefault(false.B)
   val s1_valid_masked = s1_valid && !io.cpu.s1_kill
   val s1_valid_not_nacked = s1_valid && !s1_nack
-  val s1_tlb_req_valid = RegNext(tlb_port.req.fire, false.B)
+  val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B)
   val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B)
   val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write
 
@@ -190,16 +188,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s1_req = RegEnable(s0_req, s0_clk_en)
   val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0))
 
-  val s0_tlb_req = WireInit(tlb_port.req.bits)
-  when (!tlb_port.req.fire) {
+  val s0_tlb_req = WireInit(io.tlb_port.req.bits)
+  when (!io.tlb_port.req.fire) {
     s0_tlb_req.passthrough := s0_req.phys
     s0_tlb_req.vaddr := s0_req.addr
     s0_tlb_req.size := s0_req.size
     s0_tlb_req.cmd := s0_req.cmd
     s0_tlb_req.prv := s0_req.dprv
     s0_tlb_req.v := s0_req.dv
   }
-  val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || tlb_port.req.valid)
+  val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid)
 
   val s1_read = isRead(s1_req.cmd)
   val s1_write = isWrite(s1_req.cmd)
@@ -263,7 +261,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   // address translation
   val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK
   io.ptw <> tlb.io.ptw
-  tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && tlb_port.s2_kill
+  tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill
   tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb
   tlb.io.req.bits := s1_tlb_req
   when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B }
@@ -277,8 +275,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV
   tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG
 
-  tlb_port.req.ready := clock_en_reg
-  tlb_port.s1_resp := tlb.io.resp
+  io.tlb_port.req.ready := clock_en_reg
+  io.tlb_port.s1_resp := tlb.io.resp
   when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B }
 
   pma_checker.io <> DontCare
@@ -1056,7 +1054,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     metaArb.io.out.valid || // subsumes resetting || flushing
     s1_probe || s2_probe ||
     s1_valid || s2_valid ||
-    tlb_port.req.valid ||
+    io.tlb_port.req.valid ||
     s1_tlb_req_valid || s2_tlb_req_valid ||
     pstore1_held || pstore2_valid ||
     release_state =/= s_ready ||

src/main/scala/rocket/HellaCache.scala

@@ -225,6 +225,7 @@ class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {
   val cpu = Flipped(new HellaCacheIO)
   val ptw = new TLBPTWIO()
   val errors = new DCacheErrors
+  val tlb_port = new DCacheTLBPort
 }
 
 class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
@@ -272,10 +273,7 @@ trait HasHellaCache { this: BaseTile =>
   dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }
   dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }
   InModuleBody {
-    dcache.module match {
-      case module: DCacheModule => module.tlb_port := DontCare
-      case other => other
-    }
+    dcache.module.io.tlb_port := DontCare
   }
 }
 

src/main/scala/rocket/NBDcache.scala

@@ -716,15 +716,19 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   val prober = Module(new ProbeUnit)
   val mshrs = Module(new MSHRFile)
 
+  io.tlb_port.req.ready := true.B
   io.cpu.req.ready := true.B
   val s1_valid = RegNext(io.cpu.req.fire, false.B)
+  val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B)
+  val s1_tlb_req = RegEnable(io.tlb_port.req.bits, io.tlb_port.req.fire)
   val s1_req = Reg(new HellaCacheReq)
   val s1_valid_masked = s1_valid && !io.cpu.s1_kill
   val s1_replay = RegInit(false.B)
   val s1_clk_en = Reg(Bool())
   val s1_sfence = s1_req.cmd === M_SFENCE
 
   val s2_valid = RegNext(s1_valid_masked && !s1_sfence, false.B) && !io.cpu.s2_xcpt.asUInt.orR
+  val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B)
   val s2_req = Reg(new HellaCacheReq)
   val s2_replay = RegNext(s1_replay, false.B) && s2_req.cmd =/= M_FLUSH_ALL
   val s2_recycle = Wire(Bool())
@@ -751,6 +755,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   dtlb.io.req.bits.cmd := s1_req.cmd
   dtlb.io.req.bits.prv := s1_req.dprv
   dtlb.io.req.bits.v := s1_req.dv
+  when (s1_tlb_req_valid) { dtlb.io.req.bits := s1_tlb_req }
   when (!dtlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B }
 
   dtlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence
@@ -780,6 +785,8 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   }
   val s1_addr = dtlb.io.resp.paddr
 
+  io.tlb_port.s1_resp := dtlb.io.resp
+
   when (s1_clk_en) {
     s2_req.size := s1_req.size
     s2_req.signed := s1_req.signed
@@ -990,7 +997,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   amoalu.io.rhs := s2_req.data
 
   // nack it like it's hot
-  val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || io.cpu.s2_nack ||
+  val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || io.cpu.s2_nack || s1_tlb_req_valid ||
                 s1_req.addr(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready
   val s2_nack_hit = RegEnable(s1_nack, s1_valid || s1_replay)
   when (s2_nack_hit) { mshrs.io.req.valid := false.B }