Port legacy chisel code to chisel3

src/main/scala/amba/ahb/Nodes.scala

@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba.ahb
 
-import Chisel._
+import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy._

src/main/scala/amba/apb/Nodes.scala

@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba.apb
 
-import Chisel._
+import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy._

src/main/scala/amba/apb/Test.scala

@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba.apb
 
-import Chisel._
+import chisel3._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{RRTest0, RRTest1}

src/main/scala/amba/axi4/AsyncCrossing.scala

@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -83,10 +83,10 @@ class AXI4AsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
-      val in_clock  = Clock(INPUT)
-      val in_reset  = Bool(INPUT)
-      val out_clock = Clock(INPUT)
-      val out_reset = Bool(INPUT)
+      val in_clock  = Input(Clock())
+      val in_reset  = Input(Bool())
+      val out_clock = Input(Clock())
+      val out_reset = Input(Bool())
     })
 
     source.module.clock := io.in_clock

src/main/scala/amba/axi4/Buffer.scala

@@ -2,8 +2,8 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
-import chisel3.util.IrrevocableIO
+import chisel3._
+import chisel3.util.{Queue, IrrevocableIO}
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import scala.math.min

src/main/scala/amba/axi4/Delayer.scala

@@ -2,7 +2,7 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
@@ -21,11 +21,11 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
   lazy val module = new LazyModuleImp(this) {
     def feed[T <: Data](sink: IrrevocableIO[T], source: IrrevocableIO[T], noise: T): Unit = {
       // irrevocable requires that we not lower valid
-      val hold = RegInit(Bool(false))
-      when (sink.valid)  { hold := Bool(true) }
-      when (sink.fire()) { hold := Bool(false) }
+      val hold = RegInit(false.B)
+      when (sink.valid)  { hold := true.B }
+      when (sink.fire()) { hold := false.B }
 
-      val allow = hold || UInt((q * 65535.0).toInt) <= LFSRNoiseMaker(16, source.valid)
+      val allow = hold || ((q * 65535.0).toInt).U <= LFSRNoiseMaker(16, source.valid)
       sink.valid := source.valid && allow
       source.ready := sink.ready && allow
       sink.bits := source.bits

src/main/scala/amba/axi4/Fragmenter.scala

@@ -2,11 +2,15 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
 import chisel3.util.IrrevocableIO
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
+import chisel3.util.log2Ceil
+import chisel3.util.Mux1H
+import chisel3.util.Queue
+import chisel3.util.UIntToOH
 
 case object AXI4FragLast extends ControlKey[Bool]("real_last")
 case class AXI4FragLastField() extends SimpleBundleField(AXI4FragLast)(Output(Bool()), false.B)
@@ -57,14 +61,14 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       def fragment(a: IrrevocableIO[AXI4BundleA], supportedSizes1: Seq[Int]): (IrrevocableIO[AXI4BundleA], Bool, UInt) = {
         val out = Wire(a)
 
-        val busy   = RegInit(Bool(false))
-        val r_addr = Reg(UInt(width = a.bits.params.addrBits))
-        val r_len  = Reg(UInt(width = AXI4Parameters.lenBits))
+        val busy   = RegInit(false.B)
+        val r_addr = Reg(UInt(a.bits.params.addrBits.W))
+        val r_len  = Reg(UInt(AXI4Parameters.lenBits.W))
 
         val len  = Mux(busy, r_len,  a.bits.len)
         val addr = Mux(busy, r_addr, a.bits.addr)
 
-        val lo = if (lgBytes == 0) UInt(0) else addr(lgBytes-1, 0)
+        val lo = if (lgBytes == 0) 0.U else addr(lgBytes-1, 0)
         val cutoff = AXI4Parameters.lenBits + lgBytes
         val alignment = addr((a.bits.params.addrBits min cutoff)-1, lgBytes)
 
@@ -73,7 +77,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
         val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
         val reductionMask = AddressDecoder(sizes1.values.toList)
         val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address
-          (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), UInt(v))
+          (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), v.U)
         })
 
         /* We need to compute the largest transfer allowed by the AXI len.
@@ -90,16 +94,16 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
         // Things that cause us to degenerate to a single beat
         val fixed = a.bits.burst === AXI4Parameters.BURST_FIXED
-        val narrow = a.bits.size =/= UInt(lgBytes)
+        val narrow = a.bits.size =/= lgBytes.U
         val bad = fixed || narrow
 
         // The number of beats-1 to execute
-        val beats1 = Mux(bad, UInt(0), maxSupported1)
+        val beats1 = Mux(bad, 0.U, maxSupported1)
         val beats = OH1ToOH(beats1) // beats1 + 1
 
         val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
         val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
-        val mux_addr = Wire(init = inc_addr)
+        val mux_addr = WireInit(inc_addr)
         when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
           mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)
         }
@@ -147,11 +151,11 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       out.ar.bits.echo(AXI4FragLast) := ar_last
 
       // When does W channel start counting a new transfer
-      val wbeats_latched = RegInit(Bool(false))
+      val wbeats_latched = RegInit(false.B)
       val wbeats_ready = Wire(Bool())
       val wbeats_valid = Wire(Bool())
-      when (wbeats_valid && wbeats_ready) { wbeats_latched := Bool(true) }
-      when (out.aw.fire()) { wbeats_latched := Bool(false) }
+      when (wbeats_valid && wbeats_ready) { wbeats_latched := true.B }
+      when (out.aw.fire()) { wbeats_latched := false.B }
 
       // AW flow control
       out.aw.valid := in_aw.valid && (wbeats_ready || wbeats_latched)
@@ -161,12 +165,12 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       out.aw.bits.echo(AXI4FragLast) := aw_last
 
       // We need to inject 'last' into the W channel fragments, count!
-      val w_counter = RegInit(UInt(0, width = AXI4Parameters.lenBits+1))
-      val w_idle = w_counter === UInt(0)
-      val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, UInt(0)), w_counter)
-      val w_last = w_todo === UInt(1)
+      val w_counter = RegInit(0.U((AXI4Parameters.lenBits+1).W))
+      val w_idle = w_counter === 0.U
+      val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, 0.U), w_counter)
+      val w_last = w_todo === 1.U
       w_counter := w_todo - out.w.fire()
-      assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible
+      assert (!out.w.fire() || w_todo =/= 0.U) // underflow impossible
 
       // W flow control
       wbeats_ready := w_idle
@@ -189,10 +193,10 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
       out.b.ready := in.b.ready || !b_last
 
       // Merge errors from dropped B responses
-      val error = RegInit(Vec.fill(edgeIn.master.endId) { UInt(0, width = AXI4Parameters.respBits)})
+      val error = RegInit(Vec(edgeIn.master.endId, 0.U(AXI4Parameters.respBits.W)))
       in.b.bits.resp := out.b.bits.resp | error(out.b.bits.id)
       (error zip UIntToOH(out.b.bits.id, edgeIn.master.endId).asBools) foreach { case (reg, sel) =>
-        when (sel && out.b.fire()) { reg := Mux(b_last, UInt(0), reg | out.b.bits.resp) }
+        when (sel && out.b.fire()) { reg := Mux(b_last, 0.U, reg | out.b.bits.resp) }
       }
     }
   }

src/main/scala/amba/axi4/IdIndexer.scala

@@ -2,13 +2,15 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
+import chisel3.util.log2Ceil
+import chisel3.util.Cat
 
 case object AXI4ExtraId extends ControlKey[UInt]("extra_id")
-case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(UInt(OUTPUT, width = width), UInt(0))
+case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(Output(UInt(width.W)), 0.U)
 
 /** This adapter limits the set of FIFO domain ids used by outbound transactions.
   *
@@ -71,8 +73,8 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
         out.aw.bits.echo(AXI4ExtraId) := in.aw.bits.id >> idBits
         // Special care is needed in case of 0 idBits, b/c .id has width 1 still
         if (idBits == 0) {
-          out.ar.bits.id := UInt(0)
-          out.aw.bits.id := UInt(0)
+          out.ar.bits.id := 0.U
+          out.aw.bits.id := 0.U
           in.r.bits.id := out.r.bits.echo(AXI4ExtraId)
           in.b.bits.id := out.b.bits.echo(AXI4ExtraId)
         } else {

src/main/scala/amba/axi4/Parameters.scala

@@ -2,12 +2,14 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import scala.math.max
+import chisel3.util.isPow2
+import chisel3.util.log2Up
 
 /**
   * Parameters for AXI4 slave

src/main/scala/amba/axi4/RegisterRouter.scala

@@ -2,15 +2,16 @@
 
 package freechips.rocketchip.amba.axi4
 
-import Chisel._
+import chisel3._
+import chisel3.util._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
 import freechips.rocketchip.util._
 
 case object AXI4RRId extends ControlKey[UInt]("extra_id")
-case class AXI4RRIdField(width: Int) extends SimpleBundleField(AXI4RRId)(UInt(OUTPUT, width = 1 max width), UInt(0))
+case class AXI4RRIdField(width: Int) extends SimpleBundleField(AXI4RRId)(UInt((1 max width).W), 0.U)
 
 case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)(implicit valName: ValName)
   extends SinkNode(AXI4Imp)(Seq(AXI4SlavePortParameters(
@@ -72,7 +73,7 @@ case class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes
 
     r.bits.id   := out.bits.extra(AXI4RRId)
     r.bits.data := out.bits.data
-    r.bits.last := Bool(true)
+    r.bits.last := true.B
     r.bits.resp := AXI4Parameters.RESP_OKAY
     r.bits.echo :<= out.bits.extra