Skip to content

Commit

Permalink
PTWResp gpa_is_pte, now that resp_gf can be set by stage-2 page-fault
Browse files Browse the repository at this point in the history
  • Loading branch information
ingallsj committed Jan 19, 2022
1 parent ede5841 commit 58635ec
Show file tree
Hide file tree
Showing 2 changed files with 5 additions and 3 deletions.
2 changes: 2 additions & 0 deletions src/main/scala/rocket/PTW.scala
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
val fragmented_superpage = Bool()
val homogeneous = Bool()
val gpa = Valid(UInt(vaddrBits.W))
val gpa_is_pte = Bool()
}

class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
Expand Down Expand Up @@ -399,6 +400,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa
io.requestor(i).resp.bits.gpa.bits :=
Cat(Mux(!stage2_final || !r_req.vstage1 || aux_count === (pgLevels - 1), aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff)
io.requestor(i).resp.bits.gpa_is_pte := !stage2_final
io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).hgatp := io.dpath.hgatp
io.requestor(i).vsatp := io.dpath.vsatp
Expand Down
6 changes: 3 additions & 3 deletions src/main/scala/rocket/TLB.scala
Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val r_gpa_valid = Reg(Bool())
val r_gpa = Reg(UInt(vaddrBits.W))
val r_gpa_vpn = Reg(UInt(vpnBits.W))
val r_gpa_gf = Reg(Bool())
val r_gpa_is_pte = Reg(Bool())

val priv = io.req.bits.prv
val priv_v = usingHypervisor && io.req.bits.v
Expand Down Expand Up @@ -304,7 +304,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T

r_gpa_valid := io.ptw.resp.bits.gpa.valid
r_gpa := io.ptw.resp.bits.gpa.bits
r_gpa_gf := io.ptw.resp.bits.gf
r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte
}

val entries = all_entries.map(_.getData(vpn))
Expand Down Expand Up @@ -436,7 +436,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
io.resp.miss := do_refill || vsatp_mode_mismatch || tlb_miss || multipleHits
io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0))
io.resp.gpa_is_pte := vstage1_en && r_gpa_gf
io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte
io.resp.gpa := {
val page = Mux(!vstage1_en, Cat(bad_va, vpn), r_gpa >> pgIdxBits)
val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0))
Expand Down

0 comments on commit 58635ec

Please sign in to comment.