Merge pull request #3665 from chipsalliance/v_exts

Support vector extensions

src/main/scala/rocket/RocketCore.scala

@@ -71,6 +71,7 @@ case class RocketCoreParams(
   override def eLen = vector.map(_.eLen).getOrElse(0)
   override def vfLen = vector.map(_.vfLen).getOrElse(0)
   override def vfh = vector.map(_.vfh).getOrElse(false)
+  override def vExts = vector.map(_.vExts).getOrElse(Nil)
   override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
   override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
   override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)

src/main/scala/rocket/VectorUnit.scala

@@ -16,7 +16,8 @@ case class RocketCoreVectorParams(
   vMemDataBits: Int,
   decoder: Parameters => RocketVectorDecoder,
   useDCache: Boolean,
-  issueVConfig: Boolean
+  issueVConfig: Boolean,
+  vExts: Seq[String]
 )
 
 class VectorCoreIO(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/tile/BaseTile.scala

@@ -125,7 +125,7 @@ trait HasNonDiplomaticTileParameters {
       Option.when(tileParams.core.useConditionalZero)(Seq("zicond")) ++
       Some(Seq("zicsr", "zifencei", "zihpm")) ++
       Option.when(tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen >= 16 && tileParams.core.fpu.get.minFLen <= 16)(Seq("zfh")) ++
-      zvl ++ zve ++ zvfh ++
+      zvl ++ zve ++ zvfh ++ Some(tileParams.core.vExts) ++
       tileParams.core.customIsaExt.map(Seq(_))
     ).flatten
     val multiLetterString = multiLetterExt.mkString("_")

src/main/scala/tile/Core.scala

@@ -69,6 +69,7 @@ trait CoreParams {
   def eLen: Int = 0
   def vfLen: Int = 0
   def vfh: Boolean = false
+  def vExts: Seq[String] = Nil
   def hasV: Boolean = vLen >= 128 && eLen >= 64 && vfLen >= 64
   def vMemDataBits: Int = 0
 }