CSR mcountinhibit (#2693)

* CSR mcountinhibit * mcountinhibit bit [1] is tied zero * CSR.firstHPM
chipsalliance · Nov 3, 2020 · 2040099 · 2040099
1 parent 4074969
commit 2040099
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Showing 3 changed files with 14 additions and 7 deletions.
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
@@ -419,11 +419,14 @@ class CSRFile(
   val reg_vxsat = usingVector.option(Reg(Bool()))
   val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
 
-  val reg_instret = WideCounter(64, io.retire)
-  val reg_cycle = if (enableCommitLog) reg_instret else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall) }
+  val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
+  val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
+  val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire,     inhibit = reg_mcountinhibit(0))
+    else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
   val reg_hpmevent = io.counters.map(c => Reg(init = UInt(0, xLen)))
-  (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
-  val reg_hpmcounter = io.counters.map(c => WideCounter(CSR.hpmWidth, c.inc, reset = false))
+    (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
+  val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>
+    WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }
 
   val mip = Wire(init=reg_mip)
   mip.lip := (io.interrupts.lip: Seq[Bool])
@@ -517,6 +520,7 @@ class CSRFile(
   read_mapping ++= vector_csrs
 
   if (coreParams.haveBasicCounters) {
+    read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit
     read_mapping += CSRs.mcycle -> reg_cycle
     read_mapping += CSRs.minstret -> reg_instret
 
@@ -893,6 +897,7 @@ class CSRFile(
       when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
     }
     if (coreParams.haveBasicCounters) {
+      when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) }  // mcountinhibit bit [1] is tied zero
       writeCounter(CSRs.mcycle, reg_cycle, wdata)
       writeCounter(CSRs.minstret, reg_instret, wdata)
     }

diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala
@@ -1062,6 +1062,7 @@ object CSRs {
   val mhpmcounter29 = 0xb1d
   val mhpmcounter30 = 0xb1e
   val mhpmcounter31 = 0xb1f
+  val mcountinhibit = 0x320
   val mhpmevent3 = 0x323
   val mhpmevent4 = 0x324
   val mhpmevent5 = 0x325
@@ -1322,6 +1323,7 @@ object CSRs {
     res += mhpmcounter29
     res += mhpmcounter30
     res += mhpmcounter31
+    res += mcountinhibit
     res += mhpmevent3
     res += mhpmevent4
     res += mhpmevent5

diff --git a/src/main/scala/util/Counters.scala b/src/main/scala/util/Counters.scala
@@ -38,17 +38,17 @@ object TwoWayCounter {
 }
 
 // a counter that clock gates most of its MSBs using the LSB carry-out
-case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
+case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true, inhibit: Bool = false.B)
 {
   private val isWide = width > 2*inc.getWidth
   private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
   private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
   private val nextSmall = small +& inc
-  small := nextSmall
+  when (!inhibit) { small := nextSmall }
 
   private val large = if (isWide) {
     val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
-    when (nextSmall(smallWidth)) { r := r + UInt(1) }
+    when (nextSmall(smallWidth) && !inhibit) { r := r + UInt(1) }
     r
   } else null