Fix vsetvl

chipsalliance · Jan 23, 2024 · 203fc1f · 203fc1f
1 parent 56a4da7
commit 203fc1f
Showing 1 changed file with 6 additions and 1 deletion.
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
@@ -472,7 +472,12 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S)))
 
   val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
-    val ex_avl = Mux(ex_ctrl.rxs1, ex_rs(0), ex_reg_inst(19,15))
+    val ex_avl = Mux(ex_ctrl.rxs1,
+      Mux(ex_reg_inst(19,15) === 0.U,
+        Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ~(0.U(log2Ceil(maxVLMax).W))),
+        ex_rs(0)
+      ),
+      ex_reg_inst(19,15))
     val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(
       ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),
       !ex_reg_inst(31)        -> ex_reg_inst(30,20))))