PRCI: Use RecordListMap. This compiles but not sure about the foo in …

…there...

src/main/scala/prci/ClockBundles.scala

@@ -2,15 +2,20 @@
 package freechips.rocketchip.prci
 
 import chisel3._
-import freechips.rocketchip.util.HeterogeneousBag
+import freechips.rocketchip.util.RecordListMap
+import scala.collection.immutable.ListMap
+
 
 class ClockBundle(val params: ClockBundleParameters) extends Bundle
 {
   val clock = Clock()
   val reset = Reset()
 }
 
-class ClockGroupBundle(val params: ClockGroupBundleParameters, val names: Option[Seq[String]] = None) extends Bundle
+class ClockGroupBundle(val params: ClockGroupBundleParameters) extends Bundle
 {
-  val member = HeterogeneousBag(params.members.map(p => new ClockBundle(p)), names)
+  val member: RecordListMap[ClockBundle] = {
+    val nameToBundleMap = ListMap(params.members.map{p => p.name -> new ClockBundle(p)}: _*)
+    new RecordListMap(nameToBundleMap)
+  }
 }

src/main/scala/prci/ClockGroup.scala

@@ -22,7 +22,9 @@ class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
     require (node.in.size == 1)
     require (in.member.size == out.size)
 
-    (in.member zip out) foreach { case (i, o) => o := i }
+    (in.member zip out) foreach { case ((iName, i) , o) =>
+      o := i
+    }
   }
 }
 
@@ -47,7 +49,7 @@ class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends La
 
     require (node.in.size == 1)
     require (in.head.member.size == outputs.size)
-    in.head.member.zip(outputs).foreach { case (i, o) => o := i }
+    in.head.member.zip(outputs).foreach { case ((iName, i), (oName, o)) => o := i }
   }
 }
 
@@ -63,7 +65,7 @@ class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extend
   lazy val module = new LazyModuleImp(this) {
     val (out, _) = node.out.unzip
     val outputs = out.flatMap(_.member)
-    outputs.foreach { o => o.clock := clock; o.reset := reset }
+    outputs.foreach { o => o._2.clock := clock; o._2.reset := reset }
   }
 }
 

src/main/scala/prci/ClockNodes.scala

@@ -8,7 +8,9 @@ import freechips.rocketchip.diplomacy._
 
 object ClockImp extends SimpleNodeImp[ClockSourceParameters, ClockSinkParameters, ClockEdgeParameters, ClockBundle]
 {
-  def edge(pd: ClockSourceParameters, pu: ClockSinkParameters, p: Parameters, sourceInfo: SourceInfo) = ClockEdgeParameters(pd, pu, p, sourceInfo)
+  def edge(pd: ClockSourceParameters, pu: ClockSinkParameters, p: Parameters, sourceInfo: SourceInfo) = {
+    ClockEdgeParameters("foo", pd, pu, p, sourceInfo)
+  }
   def bundle(e: ClockEdgeParameters) = new ClockBundle(e.bundle)
   def render(e: ClockEdgeParameters) = RenderedEdge(colour = "#00cc00" /* green */)
 }
@@ -73,7 +75,7 @@ object ClockSourceNode
 object ClockGroupImp extends SimpleNodeImp[ClockGroupSourceParameters, ClockGroupSinkParameters, ClockGroupEdgeParameters, ClockGroupBundle]
 {
   def edge(pd: ClockGroupSourceParameters, pu: ClockGroupSinkParameters, p: Parameters, sourceInfo: SourceInfo) = ClockGroupEdgeParameters(pd, pu, p, sourceInfo)
-  def bundle(e: ClockGroupEdgeParameters) = new ClockGroupBundle(e.bundle, Some(e.bundle.members.zipWithIndex.map{ case (_, i) => s"${e.sink.name}_${i}"}))
+  def bundle(e: ClockGroupEdgeParameters) = new ClockGroupBundle(e.bundle)
   def render(e: ClockGroupEdgeParameters) = RenderedEdge(colour = "#00cc00" /* green */)
 }
 

src/main/scala/prci/ClockParameters.scala

@@ -2,11 +2,13 @@
 package freechips.rocketchip.prci
 
 import chisel3._
+import chisel3.experimental.IO
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{InModuleBody, ModuleValue, ValName}
-import freechips.rocketchip.util.{HeterogeneousBag}
+import freechips.rocketchip.util.RecordListMap
 import scala.math.max
+import scala.collection.immutable.ListMap
 
 // All Clock parameters specify only the PLL values required at power-on
 // Dynamic control of the PLL from software can take the values out-of-range
@@ -36,9 +38,10 @@ case class ClockSinkParameters(
   require (freqErrorPPM >= 0)
 }
 
-case class ClockBundleParameters()
+case class ClockBundleParameters(name: String)
 
 case class ClockEdgeParameters(
+  name:       String,
   source:     ClockSourceParameters,
   sink:       ClockSinkParameters,
   params:     Parameters,
@@ -51,7 +54,7 @@ case class ClockEdgeParameters(
     clock
   }
 
-  val bundle = ClockBundleParameters()
+  val bundle = ClockBundleParameters(name)
 }
 
 // ClockGroups exist as the output of a PLL
@@ -71,8 +74,8 @@ case class ClockGroupEdgeParameters(
   sourceInfo: SourceInfo)
 {
   val sourceParameters = ClockSourceParameters()
-  val members = sink.members.map { s =>
-    ClockEdgeParameters(sourceParameters, s, params, sourceInfo)
+  val members = sink.members.zipWithIndex.map { case (s, i) =>
+    ClockEdgeParameters(s"${sink.name}_${i}", sourceParameters, s, params, sourceInfo)
   }
 
   val bundle = ClockGroupBundleParameters(members.map(_.bundle))
@@ -83,25 +86,32 @@ case class ClockGroupDriverParameters(
   num: Int = 1,
   driveFn: ClockGroupDriver.DriveFn = ClockGroupDriver.driveFromImplicitClock
 ) {
-  def drive(node: ClockGroupEphemeralNode)(implicit p: Parameters, vn: ValName): ModuleValue[HeterogeneousBag[ClockGroupBundle]] = {
+  def drive(node: ClockGroupEphemeralNode)(implicit p: Parameters, vn: ValName): ModuleValue[RecordListMap[ClockGroupBundle]] = {
     driveFn(node, num, p, vn)
   }
 }
 
 object ClockGroupDriver {
-  type DriveFn = (ClockGroupEphemeralNode, Int, Parameters, ValName) => ModuleValue[HeterogeneousBag[ClockGroupBundle]]
+  type DriveFn = (ClockGroupEphemeralNode, Int, Parameters, ValName) => ModuleValue[RecordListMap[ClockGroupBundle]]
 
   def driveFromImplicitClock: DriveFn = { (groups, num, p, vn) =>
     implicit val pp = p
     val dummyClockGroupSourceNode: ClockGroupSourceNode = SimpleClockGroupSource(num)
     groups :*= dummyClockGroupSourceNode
-    InModuleBody { HeterogeneousBag[ClockGroupBundle](Nil) }
+    InModuleBody { RecordListMap[ClockGroupBundle](ListMap()) }
   }
 
-  def driveFromIOs: DriveFn = { (groups, num, p, vn) =>
+  def driveFromIOs()(implicit valName: ValName): DriveFn = { (groups, num, p, vn) =>
     implicit val pp = p
     val ioClockGroupSourceNode = ClockGroupSourceNode(List.fill(num) { ClockGroupSourceParameters() })
     groups :*= ioClockGroupSourceNode
-    InModuleBody { ioClockGroupSourceNode.makeIOs()(vn) }
+    InModuleBody {
+      val bundlesAndEdges = ioClockGroupSourceNode.out
+      val nameToBundleMap = ListMap(bundlesAndEdges.map{case (b, e) => e.sink.name -> b.cloneType}:_*)
+      val ios = IO(Flipped(new RecordListMap(nameToBundleMap)))
+      ios.suggestName(valName.name)
+      bundlesAndEdges.zip(ios).foreach { case ((bundle, edge), io) => bundle <> io._2 }
+      ios
+    }
   }
 }