Use firrtl elses in elsewhen/otherwise case emission #510
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| * false. | ||
| */ | ||
| final class WhenContext(sourceInfo: SourceInfo, cond: Bool, prevCond: => Bool, block: => Unit) { | ||
| final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block: => Unit, depth: Int = 0) { |
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Maybe label depth as firrtlDepth
| case mod: DefModule => for (cmd <- mod.commands) { | ||
| body ++= newline + emit(cmd, mod) | ||
| case mod: DefModule => { | ||
| val procMod = mod.copy(commands = processWhens(mod.commands)) |
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Preprocess chisel3 IR before emission to determing whether whens have alternatives.
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chipsalliance/firrtl#601 now transforms the code generated under this PR to have the same expanded mux tree structure as the prior when emission style. |
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I have run DC with recent rocket-chip + FPU and as far as I can tell, this PR does not cause a QoR regression. Reason why results are different from past experiments is unclear, but I think we should move forward with this. Not only does it enable the invalidate API, it also improves coverage. |
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With the added emission patch (#601) or just as is?
…On Thu, Aug 3, 2017 at 11:27 AM, Jack Koenig ***@***.***> wrote:
I have run DC with recent rocket-chip + FPU and as far as I can tell, this
PR does not cause a QoR regression. Reason why results are different from
past experiments is unclear, but I think we should move forward with this.
Not only does it enable the invalidate API, it also improves coverage.
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As is, I just merged this branch into the branch of chisel3 being used by rocket-chip, no changes to firrtl. |
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There have been lots of changes to rocket-chip in the last few weeks, especially to critical paths. I suspect these changes may have removed the problematic path(s). |
This changes Chisel3's firrtl emission to use nested firrtl
whenandelsestatements for chiselwhen,elsewhen, andotherwiseblocks.There is something of a naming confusion with 132b80e, which adds a counter to keep track of the depth of the chisel
when"level." This branch keeps track of the firrtlwhennesting with a similarly named depth, which does not hold the same value.The two features could potentially be combined, especially given that
Builder.whenDepthis only ever checked for nonzero values.Tested with chipsalliance/rocket-chip@abe344a, chipsalliance/firrtl@8f3c7d3