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Emit FIRRTL bulk connects even for "input" wires #4219

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Jul 1, 2024
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Emit FIRRTL bulk connects even for "input" wires #4219

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2 changes: 1 addition & 1 deletion core/src/main/scala/chisel3/internal/MonoConnect.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -296,7 +296,7 @@ private[chisel3] object MonoConnect {

// CASE: Context is same module that both sink node and source node are in
if ((context_mod == sink_mod) && (context_mod == source_mod)) {
sink.direction != Input
!sink_is_port || sink.direction != Input
}

// CASE: Context is same module as sink node and source node is in a child module
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11 changes: 11 additions & 0 deletions src/test/scala/chiselTests/BulkConnectSpec.scala
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Expand Up @@ -112,4 +112,15 @@ class BulkConnectSpec extends ChiselPropSpec {
chirrtl should include("connect out1[0], in1[1]")
chirrtl should include("connect out1[1], in1[0]")
}

property("Chisel should emit FIRRTL bulk connect for \"input\" wires") {
class MyBundle extends Bundle {
val foo = Input(UInt(8.W))
}
val chirrtl = ChiselStage.emitCHIRRTL(new Module {
val w1, w2 = Wire(new MyBundle)
w2 <> w1
})
chirrtl should include("connect w2, w1")
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💯

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i never thought that <> was very sound for connecting two wires, so this is no worse than before 🤷‍♀️

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Until recently, I didn't know it even could work for two wires. As I mention in #4218, it does because of the special logic to sometimes emit FIRRTL bulk connects. So that work which was intended to be purely an optimization and not API visible actually extended the <> API in some funky ways.

This PR just makes it slightly more consistent in its funkiness 😇

}
}
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