Don't warn when 0.U used as value for 0-bit BundleLit field

core/src/main/scala/chisel3/Aggregate.scala

@@ -1217,13 +1217,16 @@ abstract class Record extends Aggregate {
       case (field, value) =>
         field.width match {
           // If width is unknown, then it is set by the literal value.
-          case UnknownWidth()                 => field -> value
+          case UnknownWidth() => field -> value
           case width @ KnownWidth(widthValue) =>
-            // TODO make this a warning then an error, but for older versions, just truncate.
             val valuex = if (widthValue < value.width.get) {
+              // For legacy reasons, 0.U is 1-bit, don't warn when it comes up as a literal value for 0-bit Bundle lit field.
+              val dontWarnOnZeroDotU = widthValue == 0 && value.num == 0 && value.width.get == 1
+              if (!dontWarnOnZeroDotU) {
+                val msg = s"Literal value $value is too wide for field ${cloneFields(field)} with width $widthValue"
+                Builder.warning(Warning(WarningID.BundleLiteralValueTooWide, msg))
+              }
               // Mask the value to the width of the field.
-              val msg = s"Literal value $value is too wide for field ${cloneFields(field)} with width $widthValue"
-              Builder.warning(Warning(WarningID.BundleLiteralValueTooWide, msg))
               val mask = (BigInt(1) << widthValue) - 1
               value.cloneWithValue(value.num & mask).cloneWithWidth(width)
             } else if (widthValue > value.width.get) value.cloneWithWidth(width)

src/test/scala/chiselTests/BundleLiteralSpec.scala

@@ -358,6 +358,21 @@ class BundleLiteralSpec extends ChiselFlatSpec with Utils {
     chirrtl should include("node x = cat(UInt<4>(0he), UInt<4>(0hd))")
   }
 
+  "bundle literals with zero-width fields" should "not warn for 0.U" in {
+    class SimpleBundle extends Bundle {
+      val a = UInt(4.W)
+      val b = UInt(0.W)
+    }
+    val chirrtl = ChiselStage.emitCHIRRTL(
+      new RawModule {
+        val lit = (new SimpleBundle).Lit(_.a -> 5.U, _.b -> 0.U)
+        val x = lit.asUInt
+      },
+      args = Array("--warnings-as-errors")
+    )
+    chirrtl should include("node x = cat(UInt<4>(0h5), UInt<0>(0h0))")
+  }
+
   "partial bundle literals" should "fail to pack" in {
     ChiselStage.emitCHIRRTL {
       new RawModule {