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Remove extra bit from SRAMInterface address width #3830

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merged 3 commits into from
Feb 20, 2024
Merged

Remove extra bit from SRAMInterface address width #3830

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a2b6920
remove extra bit from addr width
debs-sifive Feb 16, 2024
2486a20
update test
debs-sifive Feb 16, 2024
b12ffd0
more test fixes
debs-sifive Feb 16, 2024
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2 changes: 1 addition & 1 deletion src/main/scala/chisel3/util/SRAM.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ class SRAMInterface[T <: Data](
s"SRAMInterface_${SRAM.portedness(numReadPorts, numWritePorts, numReadwritePorts)}${if (masked) "_masked"
else ""}}_${tpe.typeName}"

val addrWidth = log2Up(memSize + 1)
val addrWidth = log2Up(memSize)

val readPorts: Vec[MemoryReadPort[T]] = Vec(numReadPorts, new MemoryReadPort(tpe, addrWidth))
val writePorts: Vec[MemoryWritePort[T]] = Vec(numWritePorts, new MemoryWritePort(tpe, addrWidth, masked))
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2 changes: 1 addition & 1 deletion src/test/scala/chiselTests/util/SRAMSpec.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ class SRAMSpec extends ChiselFlatSpec {
chirrtl should include("module Top :")
chirrtl should include("smem sram_mem : UInt<8> [32]")
chirrtl should include(
"wire sram : { readPorts : { flip address : UInt<6>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}"
"wire sram : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}"
)

val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
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