Enforce port name uniqueness

core/src/main/scala/chisel3/RawModule.scala

@@ -43,14 +43,25 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
 
   val compileOptions = moduleCompileOptions
 
+  private[chisel3] def checkPorts(): Unit = {
+    for (port <- getModulePorts) {
+      if (port._computeName(None).isEmpty) {
+        Builder.error(
+          s"Unable to name port $port in $this, " +
+            "try making it a public field of the Module"
+        )
+      }
+    }
+  }
+
   private[chisel3] override def generateComponent(): Option[Component] = {
     require(!_closed, "Can't generate module more than once")
     _closed = true
 
     // Ports get first naming priority, since they are part of a Module's IO spec
-    namePorts()
+    checkPorts()
 
-    // Ports are named, now name everything else
+    // Now that elaboration is complete for this Module, we can finalize names
     for (id <- getIds) {
       id match {
         case id: ModuleClone[_]   => id.setRefAndPortsRef(_namespace) // special handling
@@ -70,7 +81,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
               case MemoryPortBinding(_, _) =>
                 id.forceName(default = "MPORT", _namespace)
               case PortBinding(_) =>
-                id.forceName(default = "PORT", _namespace)
+                id.forceName(default = "PORT", _namespace, true, x => ModuleIO(this, x))
               case RegBinding(_, _) =>
                 id.forceName(default = "REG", _namespace)
               case WireBinding(_, _) =>

core/src/main/scala/chisel3/internal/Builder.scala

@@ -191,11 +191,19 @@ private[chisel3] trait HasId extends InstanceId {
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Record)
-  private[chisel3] def forceName(default: => String, namespace: Namespace): Unit =
+  private[chisel3] def forceName(
+    default:    => String,
+    namespace:  Namespace,
+    errorIfDup: Boolean = false,
+    refBuilder: String => Arg = Ref(_)
+  ): Unit =
     if (_ref.isEmpty) {
-      val candidate_name = _computeName(Some(default)).get
+      val candidate_name = _computeName(Some(default).filterNot(_ => errorIfDup)).get
       val available_name = namespace.name(candidate_name)
-      setRef(Ref(available_name))
+      if (errorIfDup && (available_name != candidate_name)) {
+        Builder.error(s"Cannot have duplicate names $available_name and $candidate_name")
+      }
+      setRef(refBuilder(available_name))
       // Clear naming prefix to free memory
       naming_prefix = Nil
     }

src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala

@@ -49,7 +49,9 @@ class ProgrammaticPortsSpec extends ChiselFlatSpec with Utils {
   }
 
   "Ports" should "always win over internal components in naming" in {
-    doTest(new PortsWinTester)
+    a[ChiselException] should be thrownBy extractCause[ChiselException] {
+      doTest(new PortsWinTester)
+    }
   }
 
   "Module" should "ignore suggestName on clock and reset" in {