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Can DeadCodeElimination, CommonSubexpressionElimination, ConstantPropagation, etc. be turned off ? Any options here? I want to leave them for downflow EDA tools, 'cause my team prefer verilog/vhdl code strictly the same as original chisel code. |
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Replies: 2 comments 1 reply
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FYI: CSE seems not being able to turned off. |
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Thank you! |
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PR filed in chipsalliance/firrtl#2291, let's move discussion there. |
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FYI:
firrtl.transforms.NoConstantPropagationAnnotationfirrtl.transforms.NoDedupAnnotationCSE seems not being able to turned off.
I'll file a PR later this week.